mirror of
https://github.com/google/alioth.git
synced 2024-11-28 09:26:21 +00:00
feat(board): create devicetree for aarch64 guests
Signed-off-by: Changyuan Lyu <changyuanl@google.com>
This commit is contained in:
Changyuan Lyu
Lencerf
parent
5634465cda
commit
1c1148639e
1 changed files with 241 additions and 8 deletions
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@ -12,14 +12,20 @@
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// See the License for the specific language governing permissions and
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// limitations under the License.
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use std::collections::HashMap;
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use std::sync::Arc;
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use parking_lot::Mutex;
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use crate::arch::layout::{
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GIC_V2_CPU_INTERFACE_START, GIC_V2_DIST_START, MEM_64_START, RAM_32_SIZE, RAM_32_START,
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DEVICE_TREE_LIMIT, DEVICE_TREE_START, GIC_V2_CPU_INTERFACE_START, GIC_V2_DIST_START,
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MEM_64_START, PL011_START, RAM_32_SIZE, RAM_32_START,
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};
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use crate::arch::reg::SReg;
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use crate::board::{Board, BoardConfig, Result, VcpuGuard};
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use crate::firmware::dt::{DeviceTree, Node, PropVal};
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use crate::hv::{GicV2, Hypervisor, Vcpu, Vm};
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use crate::loader::InitState;
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use crate::loader::{ExecType, InitState};
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use crate::mem::mapped::ArcMemPages;
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use crate::mem::{AddrOpt, MemRegion, MemRegionType};
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@ -28,15 +34,17 @@ where
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V: Vm,
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{
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gic_v2: V::GicV2,
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mpidrs: Mutex<Vec<u64>>,
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}
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impl<V: Vm> ArchBoard<V> {
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pub fn new<H>(_hv: &H, vm: &V, _config: &BoardConfig) -> Result<Self>
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pub fn new<H>(_hv: &H, vm: &V, config: &BoardConfig) -> Result<Self>
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where
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H: Hypervisor<Vm = V>,
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{
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let gic_v2 = vm.create_gic_v2(GIC_V2_DIST_START, GIC_V2_CPU_INTERFACE_START)?;
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Ok(ArchBoard { gic_v2 })
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let mpidrs = Mutex::new(vec![u64::MAX; config.num_cpu as usize]);
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Ok(ArchBoard { gic_v2, mpidrs })
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}
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}
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@ -60,6 +68,7 @@ where
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pub fn init_vcpu(&self, id: u32, vcpu: &mut V::Vcpu) -> Result<()> {
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vcpu.reset(id == 0)?;
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self.arch.mpidrs.lock()[id as usize] = vcpu.get_sreg(SReg::MPIDR_EL1)?;
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Ok(())
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}
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@ -101,12 +110,236 @@ where
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unimplemented!()
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}
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pub fn create_firmware_data(&self, _init_state: &InitState) -> Result<()> {
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unimplemented!()
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}
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pub fn arch_init(&self) -> Result<()> {
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self.arch.gic_v2.init()?;
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Ok(())
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}
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fn create_chosen_node(&self, init_state: &InitState, root: &mut Node) {
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let payload = self.payload.read();
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let Some(payload) = payload.as_ref() else {
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return;
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};
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if !matches!(payload.exec_type, ExecType::Linux) {
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return;
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}
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let mut node = Node::default();
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if let Some(cmd_line) = &payload.cmd_line {
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node.props
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.insert("bootargs", PropVal::String(cmd_line.clone()));
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}
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if let Some(initramfs_range) = &init_state.initramfs {
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node.props.insert(
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"linux,initrd-start",
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PropVal::U32(initramfs_range.start as u32),
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);
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node.props
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.insert("linux,initrd-end", PropVal::U32(initramfs_range.end as u32));
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}
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node.props.insert(
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"stdout-path",
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PropVal::String(format!("/pl011@{:x}", PL011_START)),
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);
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root.nodes.insert("chosen".to_owned(), node);
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}
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pub fn create_memory_node(&self, root: &mut Node) {
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let regions = self.memory.mem_region_entries();
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for (start, region) in regions {
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if region.type_ != MemRegionType::Ram {
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continue;
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};
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let node = Node {
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props: HashMap::from([
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("device_type", PropVal::Str("memory")),
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("reg", PropVal::U64List(vec![start, region.size])),
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]),
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nodes: HashMap::new(),
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};
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root.nodes.insert(format!("memory@{start:x}"), node);
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}
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}
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pub fn create_cpu_nodes(&self, root: &mut Node) {
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let mpidrs = self.arch.mpidrs.lock();
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let mut cpu_nodes = mpidrs
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.iter()
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.map(|mpidr| {
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let reg = mpidr & 0xff_00ff_ffff;
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(
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format!("cpu@{reg}"),
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Node {
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props: HashMap::from([
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("device_type", PropVal::Str("cpu")),
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("compatible", PropVal::Str("arm,arm-v8")),
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("enable-method", PropVal::Str("psci")),
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("reg", PropVal::U32(reg as u32)),
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("phandle", PropVal::PHandle(reg as u32 | (1 << 16))),
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]),
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nodes: HashMap::new(),
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},
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)
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})
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.collect::<HashMap<_, _>>();
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let cores = mpidrs
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.iter()
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.map(|mpidr| {
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let reg = mpidr & 0xff_00ff_ffff;
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(
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format!("core{reg}"),
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Node {
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props: HashMap::from([("cpu", PropVal::PHandle(reg as u32 | (1 << 16)))]),
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nodes: HashMap::new(),
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},
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)
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})
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.collect();
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let cpu_map = Node {
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props: HashMap::new(),
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nodes: HashMap::from([(
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"socket0".to_owned(),
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Node {
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props: HashMap::new(),
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nodes: HashMap::from([(
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"cluster0".to_owned(),
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Node {
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props: HashMap::new(),
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nodes: cores,
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},
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)]),
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},
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)]),
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};
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cpu_nodes.insert("cpu-map".to_owned(), cpu_map);
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let cpus = Node {
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props: HashMap::from([
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("#address-cells", PropVal::U32(1)),
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("#size-cells", PropVal::U32(0)),
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]),
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nodes: cpu_nodes,
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};
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root.nodes.insert("cpus".to_owned(), cpus);
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}
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fn create_clock_node(&self, root: &mut Node) {
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let node = Node {
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props: HashMap::from([
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("compatible", PropVal::Str("fixed-clock")),
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("clock-frequency", PropVal::U32(24000000)),
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("clock-output-names", PropVal::Str("clk24mhz")),
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("phandle", PropVal::PHandle(PHANDLE_CLOCK)),
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("#clock-cells", PropVal::U32(0)),
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]),
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nodes: HashMap::new(),
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};
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root.nodes.insert("apb-pclk".to_owned(), node);
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}
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fn create_pl011_node(&self, root: &mut Node) {
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let pin = 1;
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let edge_trigger = 1;
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let spi = 0;
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let node = Node {
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props: HashMap::from([
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("compatible", PropVal::Str("arm,primecell\0arm,pl011")),
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("reg", PropVal::U64List(vec![PL011_START, 0x1000])),
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("interrupts", PropVal::U32List(vec![spi, pin, edge_trigger])),
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("clock-names", PropVal::Str("uartclk\0apb_pclk")),
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(
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"clocks",
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PropVal::U32List(vec![PHANDLE_CLOCK, PHANDLE_CLOCK]),
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),
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]),
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nodes: HashMap::new(),
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};
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root.nodes.insert(format!("pl011@{:x}", PL011_START), node);
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}
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// Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
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fn create_timer_node(&self, root: &mut Node) {
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let mut interrupts = vec![];
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let irq_pins = [13, 14, 11, 10];
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let ppi = 1;
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let level_trigger = 4;
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let cpu_mask = (1 << self.config.num_cpu) - 1;
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for pin in irq_pins {
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interrupts.extend([ppi, pin, cpu_mask << 8 | level_trigger]);
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}
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let node = Node {
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props: HashMap::from([
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("compatible", PropVal::Str("arm,armv8-timer")),
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("interrupts", PropVal::U32List(interrupts)),
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("always-on", PropVal::Empty),
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]),
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nodes: HashMap::new(),
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};
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root.nodes.insert("timer".to_owned(), node);
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}
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// Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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fn create_gicv2_node(&self, root: &mut Node) {
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let node = Node {
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props: HashMap::from([
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("compatible", PropVal::Str("arm,cortex-a15-gic")),
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("#interrupt-cells", PropVal::U32(3)),
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(
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"reg",
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PropVal::U64List(vec![
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GIC_V2_DIST_START,
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0x1000,
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GIC_V2_CPU_INTERFACE_START,
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0x2000,
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]),
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),
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("phandle", PropVal::U32(PHANDLE_GIC)),
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("interrupt-controller", PropVal::Empty),
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]),
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nodes: HashMap::new(),
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};
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root.nodes
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.insert(format!("intc@{GIC_V2_DIST_START:x}"), node);
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}
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// Documentation/devicetree/bindings/arm/psci.yaml
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fn create_psci_node(&self, root: &mut Node) {
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let node = Node {
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props: HashMap::from([
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("method", PropVal::Str("hvc")),
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("compatible", PropVal::Str("arm,psci-0.2\0arm,psci")),
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]),
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nodes: HashMap::new(),
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};
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root.nodes.insert("psci".to_owned(), node);
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}
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pub fn create_firmware_data(&self, init_state: &InitState) -> Result<()> {
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let mut device_tree = DeviceTree::new();
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let root = &mut device_tree.root;
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root.props.insert("#address-cells", PropVal::U32(2));
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root.props.insert("#size-cells", PropVal::U32(2));
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root.props.insert("model", PropVal::Str("linux,dummy-virt"));
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root.props
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.insert("compatible", PropVal::Str("linux,dummy-virt"));
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root.props
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.insert("interrupt-parent", PropVal::PHandle(PHANDLE_GIC));
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self.create_chosen_node(init_state, root);
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self.create_pl011_node(root);
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self.create_memory_node(root);
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self.create_cpu_nodes(root);
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self.create_gicv2_node(root);
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self.create_clock_node(root);
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self.create_timer_node(root);
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self.create_psci_node(root);
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log::debug!("device tree: {:#x?}", device_tree);
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let blob = device_tree.to_blob();
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let ram = self.memory.ram_bus();
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assert!(blob.len() as u64 <= DEVICE_TREE_LIMIT);
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ram.write_range(DEVICE_TREE_START, blob.len() as u64, &*blob)?;
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Ok(())
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}
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}
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const PHANDLE_GIC: u32 = 1;
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const PHANDLE_CLOCK: u32 = 2;
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