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refactor: move x86_64 registers to module arch

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Signed-off-by: Changyuan Lyu <changyuanl@google.com>
This commit is contained in:
Changyuan Lyu 2024-06-16 10:15:31 -07:00 committed by Lencerf
parent 54a12de6f5
commit c8e891e7e7
12 changed files with 106 additions and 126 deletions
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13
alioth/src/hv/arch/arch.rs → alioth/src/arch/x86_64/cpuid.rs
View file

@ -12,7 +12,12 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#[cfg(target_arch = "x86_64")]
pub use x86_64::*;
#[cfg(target_arch = "x86_64")]
pub mod x86_64;
#[derive(Debug, Default, Clone)]
pub struct Cpuid {
pub func: u32,
pub index: Option<u32>,
pub eax: u32,
pub ebx: u32,
pub ecx: u32,
pub edx: u32,
}

75
alioth/src/arch/x86_64/reg.rs
View file

@ -168,3 +168,78 @@ bitfield! {
pub granularity, _: 15;
pub unusable, _: 16;
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum Reg {
Rax,
Rbx,
Rcx,
Rdx,
Rsi,
Rdi,
Rsp,
Rbp,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
Rip,
Rflags,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum SReg {
Cr0,
Cr2,
Cr3,
Cr4,
Cr8,
Efer,
ApicBase,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum SegReg {
Cs,
Ds,
Es,
Fs,
Gs,
Ss,
Tr,
Ldtr,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum DtReg {
Gdtr,
Idtr,
}
#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
pub struct SegRegVal {
pub selector: u16,
pub base: u64,
pub limit: u32,
pub access: SegAccess,
}
impl SegRegVal {
pub fn to_desc(&self) -> u64 {
((self.base & 0xff00_0000) << (56 - 24))
| (((self.access.0 as u64) & 0x0000_f0ff) << 40)
| (((self.limit as u64) & 0x000f_0000) << (48 - 16))
| ((self.base & 0x00ff_ffff) << 16)
| ((self.limit as u64) & 0x0000_ffff)
}
}
#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
pub struct DtRegVal {
pub base: u64,
pub limit: u16,
}

1
alioth/src/arch/x86_64/x86_64.rs
View file

@ -12,6 +12,7 @@
// See the License for the specific language governing permissions and
// limitations under the License.
pub mod cpuid;
pub mod layout;
pub mod msr;
pub mod paging;

4
alioth/src/board/x86_64.rs
View file

@ -21,11 +21,11 @@ use std::sync::Arc;
use parking_lot::Mutex;
use zerocopy::{AsBytes, FromBytes, FromZeroes};
use crate::arch::cpuid::Cpuid;
use crate::arch::layout::{BIOS_DATA_END, EBDA_END, EBDA_START, MEM_64_START, RAM_32_SIZE};
use crate::arch::reg::SegAccess;
use crate::arch::reg::{Reg, SegAccess, SegReg, SegRegVal};
use crate::arch::sev::SnpPageType;
use crate::board::{Board, BoardConfig, Result, VcpuGuard};
use crate::hv::arch::{Cpuid, Reg, SegReg, SegRegVal};
use crate::hv::{Coco, Hypervisor, Vcpu, Vm};
use crate::loader::InitState;
use crate::mem::mapped::ArcMemPages;

100
alioth/src/hv/arch/x86_64.rs
View file

@ -1,100 +0,0 @@
// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
use crate::arch::reg::SegAccess;
#[derive(Debug, Default, Clone)]
pub struct Cpuid {
pub func: u32,
pub index: Option<u32>,
pub eax: u32,
pub ebx: u32,
pub ecx: u32,
pub edx: u32,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum Reg {
Rax,
Rbx,
Rcx,
Rdx,
Rsi,
Rdi,
Rsp,
Rbp,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
Rip,
Rflags,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum SReg {
Cr0,
Cr2,
Cr3,
Cr4,
Cr8,
Efer,
ApicBase,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum SegReg {
Cs,
Ds,
Es,
Fs,
Gs,
Ss,
Tr,
Ldtr,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum DtReg {
Gdtr,
Idtr,
}
#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
pub struct SegRegVal {
pub selector: u16,
pub base: u64,
pub limit: u32,
pub access: SegAccess,
}
impl SegRegVal {
pub fn to_desc(&self) -> u64 {
((self.base & 0xff00_0000) << (56 - 24))
| (((self.access.0 as u64) & 0x0000_f0ff) << 40)
| (((self.limit as u64) & 0x000f_0000) << (48 - 16))
| ((self.base & 0x00ff_ffff) << 16)
| ((self.limit as u64) & 0x0000_ffff)
}
}
#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
pub struct DtRegVal {
pub base: u64,
pub limit: u16,
}

9
alioth/src/hv/hv.rs
View file

@ -12,9 +12,6 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#[path = "arch/arch.rs"]
pub mod arch;
#[cfg(target_os = "linux")]
#[path = "kvm/kvm.rs"]
mod kvm;
@ -31,9 +28,11 @@ use std::os::fd::AsFd;
use std::sync::Arc;
use std::thread::JoinHandle;
use arch::Reg;
#[cfg(target_arch = "x86_64")]
use arch::{Cpuid, DtReg, DtRegVal, SReg, SegReg, SegRegVal};
use crate::arch::cpuid::Cpuid;
use crate::arch::reg::Reg;
#[cfg(target_arch = "x86_64")]
use crate::arch::reg::{DtReg, DtRegVal, SReg, SegReg, SegRegVal};
use crate::arch::sev::{SevPolicy, SnpPageType, SnpPolicy};

8
alioth/src/hv/kvm/vcpu/vcpu.rs
View file

@ -23,14 +23,16 @@ use std::ptr::null_mut;
use libc::{mmap, munmap, MAP_FAILED, MAP_SHARED, PROT_READ, PROT_WRITE};
use snafu::ResultExt;
#[cfg(target_arch = "x86_64")]
use crate::arch::cpuid::Cpuid;
use crate::arch::reg::Reg;
#[cfg(target_arch = "x86_64")]
use crate::arch::reg::{DtReg, DtRegVal, SReg, SegReg, SegRegVal};
use crate::ffi;
use crate::hv::arch::Reg;
use crate::hv::kvm::bindings::{KvmExit, KvmRun};
use crate::hv::kvm::ioctls::kvm_run;
use crate::hv::kvm::{kvm_error, KvmError};
use crate::hv::{error, Error, Vcpu, VmEntry, VmExit};
#[cfg(target_arch = "x86_64")]
use crate::hv::{Cpuid, DtReg, DtRegVal, SReg, SegReg, SegRegVal};
pub(super) struct KvmRunBlock {
addr: usize,

7
alioth/src/hv/kvm/vcpu/x86_64.rs
View file

@ -14,8 +14,8 @@
use snafu::ResultExt;
use crate::arch::reg::SegAccess;
use crate::hv::arch::{Cpuid, DtReg, DtRegVal, Reg, SReg, SegReg, SegRegVal};
use crate::arch::cpuid::Cpuid;
use crate::arch::reg::{DtReg, DtRegVal, Reg, SReg, SegAccess, SegReg, SegRegVal};
use crate::hv::kvm::bindings::{
KvmCpuid2, KvmCpuid2Flag, KvmCpuidEntry2, KvmRegs, KVM_MAX_CPUID_ENTRIES,
};
@ -312,9 +312,8 @@ mod test {
use crate::arch::msr::Efer;
use crate::arch::paging::Entry;
use crate::arch::reg::{Cr0, Cr4, SegAccess};
use crate::arch::reg::{Cr0, Cr4, Reg, SegAccess};
use crate::ffi;
use crate::hv::arch::Reg;
use crate::hv::{
DtReg, DtRegVal, Hypervisor, Kvm, MemMapOption, SReg, SegReg, SegRegVal, Vcpu, Vm, VmEntry,
VmExit, VmMemory,

3
alioth/src/loader/firmware/x86_64.rs
View file

@ -18,8 +18,7 @@ use std::path::Path;
use std::sync::Arc;
use crate::arch::layout::MEM_64_START;
use crate::arch::reg::{Cr0, Rflags, SegAccess};
use crate::hv::arch::{DtReg, DtRegVal, Reg, SReg, SegReg, SegRegVal};
use crate::arch::reg::{Cr0, DtReg, DtRegVal, Reg, Rflags, SReg, SegAccess, SegReg, SegRegVal};
use crate::loader::{InitState, Result};
use crate::mem::mapped::ArcMemPages;
use crate::mem::{AddrOpt, MemRegion, MemRegionType, Memory};

5
alioth/src/loader/linux/x86_64.rs
View file

@ -19,8 +19,9 @@ use std::path::Path;
use crate::arch::msr::Efer;
use crate::arch::paging::Entry;
use crate::arch::reg::{Cr0, Cr4, Rflags, SegAccess};
use crate::hv::arch::{DtReg, DtRegVal, Reg, SReg, SegReg, SegRegVal};
use crate::arch::reg::{
Cr0, Cr4, DtReg, DtRegVal, Reg, Rflags, SReg, SegAccess, SegReg, SegRegVal,
};
use crate::mem::mapped::RamBus;
use zerocopy::{AsBytes, FromZeroes};

4
alioth/src/loader/loader.rs
View file

@ -17,9 +17,9 @@ use std::path::PathBuf;
use thiserror::Error;
use crate::hv::arch::Reg;
use crate::arch::reg::Reg;
#[cfg(target_arch = "x86_64")]
use crate::hv::arch::{DtReg, DtRegVal, SReg, SegReg, SegRegVal};
use crate::arch::reg::{DtReg, DtRegVal, SReg, SegReg, SegRegVal};
use crate::mem::{MemRegionEntry, MemRegionType};
pub mod elf;

3
alioth/src/loader/xen/xen.rs
View file

@ -23,8 +23,7 @@ use crate::align_up;
use crate::arch::layout::{
BOOT_GDT_START, EBDA_START, HVM_START_INFO_START, KERNEL_CMD_LINE_LIMIT, KERNEL_CMD_LINE_START,
};
use crate::arch::reg::{Cr0, Rflags, SegAccess};
use crate::hv::arch::{DtReg, DtRegVal, Reg, SReg, SegReg, SegRegVal};
use crate::arch::reg::{Cr0, DtReg, DtRegVal, Reg, Rflags, SReg, SegAccess, SegReg, SegRegVal};
use crate::loader::elf::{
Elf64Header, Elf64Note, Elf64ProgramHeader, Elf64SectionHeader, ELF_HEADER_MAGIC,
ELF_IDENT_CLASS_64, ELF_IDENT_LITTLE_ENDIAN, PT_NOTE, SHT_NOTE,