Pcie: let PcieRootPort determine bridge's PciAddress

Currently bridge's PciAddress is allocated from system bus allocator,
but when virtual pcie root port is linked to physical pcie root port,
its PciAddress should be same as physical pcie RP, so thid commit let
bridge get its PciAddress from the backend pcie RP device, this is
convenient for later pcie root port.

This commit doesn't change function.

BUG=b:185084350
TEST=tools/presubmit

Change-Id: I2b81f6447898bd76758569095aa48f3daa2b0dcc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3423458
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>

devices/src/pci/pcie/pci_bridge.rs

@@ -145,19 +145,9 @@ impl PciDevice for PciBridge {
         &mut self,
         resources: &mut SystemAllocator,
     ) -> std::result::Result<PciAddress, PciDeviceError> {
-        if self.pci_address.is_none() {
-            self.pci_address =
-                match resources.allocate_pci(self.bus_range.primary, self.debug_label()) {
-                    Some(Alloc::PciBar {
-                        bus,
-                        dev,
-                        func,
-                        bar: _,
-                    }) => Some(PciAddress { bus, dev, func }),
-                    _ => None,
-                }
-        }
-        self.pci_address.ok_or(PciDeviceError::PciAllocationFailed)
+        let address = self.device.lock().allocate_address(resources)?;
+        self.pci_address = Some(address);
+        Ok(address)
     }
 
     fn keep_rds(&self) -> Vec<RawDescriptor> {

devices/src/pci/pcie/pcie_device.rs

@@ -7,12 +7,17 @@ use sync::Mutex;
 use crate::pci::pci_configuration::PciCapabilityID;
 use crate::pci::pcie::pci_bridge::PciBridgeBusRange;
 use crate::pci::pcie::*;
-use crate::pci::{MsixConfig, PciAddress, PciCapability};
+use crate::pci::{MsixConfig, PciAddress, PciCapability, PciDeviceError};
 use data_model::DataInit;
+use resources::SystemAllocator;
 
 pub trait PcieDevice: Send {
     fn get_device_id(&self) -> u16;
     fn debug_label(&self) -> String;
+    fn allocate_address(
+        &mut self,
+        resources: &mut SystemAllocator,
+    ) -> std::result::Result<PciAddress, PciDeviceError>;
     fn read_config(&self, reg_idx: usize, data: &mut u32);
     fn write_config(&mut self, reg_idx: usize, offset: u64, data: &[u8]);
     fn clone_interrupt(&mut self, msix_config: Arc<Mutex<MsixConfig>>);

devices/src/pci/pcie/pcie_rp.rs

@@ -6,13 +6,14 @@ use sync::Mutex;
 
 use crate::bus::{HostHotPlugKey, HotPlugBus};
 use crate::pci::pci_configuration::PciCapabilityID;
-use crate::pci::{MsixConfig, PciAddress, PciCapability};
+use crate::pci::{MsixConfig, PciAddress, PciCapability, PciDeviceError};
 
 use crate::pci::pcie::pci_bridge::PciBridgeBusRange;
 use crate::pci::pcie::pcie_device::{PcieCap, PcieDevice};
 use crate::pci::pcie::*;
 use base::warn;
 use data_model::DataInit;
+use resources::{Alloc, SystemAllocator};
 
 // reserve 8MB memory window
 const PCIE_RP_BR_MEM_SIZE: u64 = 0x80_0000;
@@ -23,6 +24,7 @@ const PCIE_RP_DID: u16 = 0x3420;
 pub struct PcieRootPort {
     pcie_cap_reg_idx: Option<usize>,
     msix_config: Option<Arc<Mutex<MsixConfig>>>,
+    pci_address: Option<PciAddress>,
     slot_control: u16,
     slot_status: u16,
     bus_range: PciBridgeBusRange,
@@ -41,6 +43,7 @@ impl PcieRootPort {
         PcieRootPort {
             pcie_cap_reg_idx: None,
             msix_config: None,
+            pci_address: None,
             slot_control: PCIE_SLTCTL_PIC_OFF | PCIE_SLTCTL_AIC_OFF,
             slot_status: 0,
             bus_range,
@@ -146,6 +149,25 @@ impl PcieDevice for PcieRootPort {
         "PcieRootPort".to_string()
     }
 
+    fn allocate_address(
+        &mut self,
+        resources: &mut SystemAllocator,
+    ) -> std::result::Result<PciAddress, PciDeviceError> {
+        if self.pci_address.is_none() {
+            self.pci_address =
+                match resources.allocate_pci(self.bus_range.primary, self.debug_label()) {
+                    Some(Alloc::PciBar {
+                        bus,
+                        dev,
+                        func,
+                        bar: _,
+                    }) => Some(PciAddress { bus, dev, func }),
+                    _ => None,
+                }
+        }
+        self.pci_address.ok_or(PciDeviceError::PciAllocationFailed)
+    }
+
     fn clone_interrupt(&mut self, msix_config: Arc<Mutex<MsixConfig>>) {
         self.msix_config = Some(msix_config);
     }