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hypervisor: update CpuIdEntry uses for haxm and whpx

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The haxm and whpx features aren't enabled by default, so these weren't
caught by the tests.

BUG=None
TEST=win64=["whpx", "haxm"] in Cargo.toml
TEST=tools/run_tests --target=host --arch=win64 --build-only

Fixes: 6af7ff8540 ("crosvm: Pass down CpuidResult instead.")
Change-Id: I72bc9bd1c78849be4f47e57a36a1fb02332041f2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3723803
Reviewed-by: Noah Gold <nkgold@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
This commit is contained in:
Daniel Verkamp 2022-06-24 16:46:48 -07:00 committed by Chromeos LUCI
parent 44fd232dbc
commit 2d2eec381b
5 changed files with 74 additions and 61 deletions
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52
hypervisor/src/haxm.rs
View file

@ -2,7 +2,7 @@
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
use std::arch::x86_64::__cpuid;
use std::arch::x86_64::{CpuidResult, __cpuid};
use std::sync::atomic::{AtomicBool, Ordering};
use base::{AsRawDescriptor, RawDescriptor, Result, SafeDescriptor};
@ -155,46 +155,56 @@ impl HypervisorX86_64 for Haxm {
function: 0x1,
index: 0,
flags: 0,
eax: 0,
ebx: 0,
ecx: supported_features_1_ecx,
edx: supported_features_1_edx,
cpuid: CpuidResult {
eax: 0,
ebx: 0,
ecx: supported_features_1_ecx,
edx: supported_features_1_edx,
},
},
CpuIdEntry {
function: 0x7,
index: 0,
flags: 0,
eax: cpuid_7.eax,
ebx: cpuid_7.ebx,
ecx: cpuid_7.ecx,
edx: cpuid_7.edx,
cpuid: CpuidResult {
eax: cpuid_7.eax,
ebx: cpuid_7.ebx,
ecx: cpuid_7.ecx,
edx: cpuid_7.edx,
},
},
CpuIdEntry {
function: 0x15,
index: 0,
flags: 0,
eax: cpuid_15.eax,
ebx: cpuid_15.ebx,
ecx: cpuid_15.ecx,
edx: cpuid_15.edx,
cpuid: CpuidResult {
eax: cpuid_15.eax,
ebx: cpuid_15.ebx,
ecx: cpuid_15.ecx,
edx: cpuid_15.edx,
},
},
CpuIdEntry {
function: 0x16,
index: 0,
flags: 0,
eax: cpuid_16.eax,
ebx: cpuid_16.ebx,
ecx: cpuid_16.ecx,
edx: cpuid_16.edx,
cpuid: CpuidResult {
eax: cpuid_16.eax,
ebx: cpuid_16.ebx,
ecx: cpuid_16.ecx,
edx: cpuid_16.edx,
},
},
CpuIdEntry {
function: 0x80000001,
index: 0,
flags: 0,
eax: 0,
ebx: 0,
ecx: supported_features_80000001_ecx,
edx: supported_features_80000001_edx,
cpuid: CpuidResult {
eax: 0,
ebx: 0,
ecx: supported_features_80000001_ecx,
edx: supported_features_80000001_edx,
},
},
],
})

19
hypervisor/src/haxm/vcpu.rs
View file

@ -4,6 +4,7 @@
use core::ffi::c_void;
use libc::{EINVAL, ENOENT, ENOSPC, ENXIO};
use std::arch::x86_64::CpuidResult;
use std::cmp::min;
use std::intrinsics::copy_nonoverlapping;
use std::mem::{size_of, ManuallyDrop};
@ -934,10 +935,12 @@ impl From<&hax_cpuid_entry> for CpuIdEntry {
function: item.function,
index: item.index,
flags: item.flags,
eax: item.eax,
ebx: item.ebx,
ecx: item.ecx,
edx: item.edx,
cpuid: CpuidResult {
eax: item.eax,
ebx: item.ebx,
ecx: item.ecx,
edx: item.edx,
},
}
}
}
@ -948,10 +951,10 @@ impl From<&CpuIdEntry> for hax_cpuid_entry {
function: item.function,
index: item.index,
flags: item.flags,
eax: item.eax,
ebx: item.ebx,
ecx: item.ecx,
edx: item.edx,
eax: item.cpuid.eax,
ebx: item.cpuid.ebx,
ecx: item.cpuid.ecx,
edx: item.cpuid.edx,
pad: Default::default(),
}
}

5
hypervisor/src/whpx.rs
View file

@ -190,10 +190,7 @@ fn cpuid_entry_from_host(function: u32, index: u32) -> CpuIdEntry {
function,
index,
flags: 0,
eax: result.eax,
ebx: result.ebx,
ecx: result.ecx,
edx: result.edx,
cpuid: result,
}
}

8
hypervisor/src/whpx/types.rs
View file

@ -720,10 +720,10 @@ impl From<&CpuIdEntry> for WHV_X64_CPUID_RESULT {
fn from(entry: &CpuIdEntry) -> Self {
WHV_X64_CPUID_RESULT {
Function: entry.function,
Eax: entry.eax,
Ebx: entry.ebx,
Ecx: entry.ecx,
Edx: entry.edx,
Eax: entry.cpuid.eax,
Ebx: entry.cpuid.ebx,
Ecx: entry.cpuid.ecx,
Edx: entry.cpuid.edx,
..Default::default()
}
}

51
hypervisor/src/whpx/vcpu.rs
View file

@ -4,6 +4,7 @@
use core::ffi::c_void;
use libc::{EBUSY, EINVAL, ENOENT, ENXIO};
use std::arch::x86_64::CpuidResult;
use std::cell::RefCell;
use std::convert::TryInto;
use std::mem::size_of;
@ -786,26 +787,28 @@ impl Vcpu for WhpxVcpu {
function: self.last_exit_context.__bindgen_anon_1.CpuidAccess.Rax as u32,
index: self.last_exit_context.__bindgen_anon_1.CpuidAccess.Rcx as u32,
flags: 0,
eax: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRax as u32,
ebx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRbx as u32,
ecx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRcx as u32,
edx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRdx as u32,
cpuid: CpuidResult {
eax: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRax as u32,
ebx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRbx as u32,
ecx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRcx as u32,
edx: self
.last_exit_context
.__bindgen_anon_1
.CpuidAccess
.DefaultResultRdx as u32,
},
}
};
Ok(VcpuExit::Cpuid { entry })
@ -1199,16 +1202,16 @@ impl VcpuX86_64 for WhpxVcpu {
let values = vec![
WHV_REGISTER_VALUE { Reg64: rip },
WHV_REGISTER_VALUE {
Reg64: entry.eax as u64,
Reg64: entry.cpuid.eax as u64,
},
WHV_REGISTER_VALUE {
Reg64: entry.ebx as u64,
Reg64: entry.cpuid.ebx as u64,
},
WHV_REGISTER_VALUE {
Reg64: entry.ecx as u64,
Reg64: entry.cpuid.ecx as u64,
},
WHV_REGISTER_VALUE {
Reg64: entry.edx as u64,
Reg64: entry.cpuid.edx as u64,
},
];