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x86_64: remove --features=direct memory layout

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Always use the standard memory layout now that we are removing support
for the "direct" feature.

BUG=b:279218487
TEST=tools/dev_container tools/presubmit

Change-Id: Ic5b7a31d7bbc7715494c3c62126662023b50eb0b
Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/4550407
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
This commit is contained in:
Daniel Verkamp 2023-05-22 12:40:08 -07:00 committed by crosvm LUCI
parent 33eca5556d
commit 5263540f6c
2 changed files with 6 additions and 30 deletions
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6
docs/book/src/appendix/memory_layout.md
View file

@ -2,11 +2,12 @@
## x86-64 guest physical memory map
This is a survey of the existing memory layout for crosvm on x86-64 when booting a Linux kernel. Some of these values are different when booting a BIOS image or when compiled with features=direct (ManaTEE); see the source. All addresses are in hexadecimal.
This is a survey of the existing memory layout for crosvm on x86-64 when booting a Linux kernel. Some of these values are different when booting a BIOS image;
see the source. All addresses are in hexadecimal.
| Name/source link | Address | End (exclusive) | Size | Notes |
| ---------------------------- | ------------- | --------------- | --------- | ---------------------------------------------------------------------------------------- |
| | `0000` | `7000` | | RAM (may start at 0x1000 for crosvm-direct) |
| [`START_OF_RAM_32BITS`] | `0000` | | | RAM |
| [`ZERO_PAGE_OFFSET`] | `7000` | | | Linux boot_params structure |
| [`BOOT_STACK_POINTER`] | `8000` | | | Boot SP value |
| [`boot_pml4_addr`] | `9000` | | | Boot page table |
@ -25,6 +26,7 @@ This is a survey of the existing memory layout for crosvm on x86-64 when booting
| | `1_0000_0000` | | | RAM (>4G) |
| | (end of RAM) | | | High (>4G) MMIO allocation area |
[`start_of_ram_32bits`]: https://crsrc.org/o/src/platform/crosvm/x86_64/src/lib.rs;l=335?q=START_OF_RAM_32BITS
[`zero_page_offset`]: https://crsrc.org/o/src/platform/crosvm/x86_64/src/lib.rs;l=338?q=ZERO_PAGE_OFFSET
[`boot_stack_pointer`]: https://crsrc.org/o/src/platform/crosvm/x86_64/src/lib.rs;l=332?q=BOOT_STACK_POINTER
[`boot_pml4_addr`]: https://crsrc.org/o/src/platform/crosvm/x86_64/src/regs.rs;l=299?q=boot_pml4_addr

30
x86_64/src/lib.rs
View file

@ -332,7 +332,7 @@ const MB: u64 = 1 << 20;
const GB: u64 = 1 << 30;
pub const BOOT_STACK_POINTER: u64 = 0x8000;
const START_OF_RAM_32BITS: u64 = if cfg!(feature = "direct") { 0x1000 } else { 0 };
const START_OF_RAM_32BITS: u64 = 0;
const FIRST_ADDR_PAST_32BITS: u64 = 1 << 32;
// Linux (with 4-level paging) has a physical memory limit of 46 bits (64 TiB).
const HIGH_MMIO_MAX_END: u64 = (1u64 << 46) - 1;
@ -382,17 +382,7 @@ static LOW_MEMORY_LAYOUT: OnceCell<LowMemoryLayout> = OnceCell::new();
pub fn init_low_memory_layout(pcie_ecam: Option<AddressRange>, pci_low_start: Option<u64>) {
LOW_MEMORY_LAYOUT.get_or_init(|| {
// Make sure it align to 256MB for MTRR convenient
const MEM_32BIT_GAP_SIZE: u64 = if cfg!(feature = "direct") {
// Allow space for identity mapping coreboot memory regions on the host
// which is found at around 7a00_0000 (little bit before 2GB)
//
// TODO(b/188011323): stop hardcoding sizes and addresses here and instead
// determine the memory map from how the VM has been configured via the
// command line.
2560 * MB
} else {
768 * MB
};
const MEM_32BIT_GAP_SIZE: u64 = 768 * MB;
// Reserved memory for nand_bios/LAPIC/IOAPIC/HPET/.....
const RESERVED_MEM_SIZE: u64 = 0x800_0000;
const PCI_MMIO_END: u64 = FIRST_ADDR_PAST_32BITS - RESERVED_MEM_SIZE - 1;
@ -2376,22 +2366,6 @@ mod tests {
assert_eq!(read_pcie_cfg_mmio().len().unwrap(), 256 * MB);
}
#[test]
#[cfg(feature = "direct")]
#[ignore] // TODO(b/236253615): Fix and re-enable this test.
fn end_addr_before_32bits() {
setup();
// On volteer, type16 (coreboot) region is at 0x00000000769f3000-0x0000000076ffffff.
// On brya, type16 region is at 0x0000000076876000-0x00000000803fffff
let brya_type16_address = 0x7687_6000;
assert!(
read_pci_mmio_before_32bit().start < brya_type16_address,
"{} < {}",
read_pci_mmio_before_32bit().start,
brya_type16_address
);
}
#[test]
fn check_32bit_gap_size_alignment() {
setup();