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Revert "x86_64: remove special-case mappings for direct"

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This reverts commit 052f7df430.

Reason for revert: breaks tast.health.DiagnosticsRun.cpu_cache on volteer-manatee

Original change's description:
> x86_64: remove special-case mappings for direct
>
> Now that we can handle file-backed mappings that overlap with guest
> memory, we can remove the workarounds for coreboot regions when
> compiling with --features=direct.
>
> BUG=b:188011323
> TEST=cargo test -p x86_64 --features=direct
> TEST=Boot volteer-manatee and brya-manatee
>
> Change-Id: I9ac2a25e1896c5ec61bd302882d4c99d8b36b0dd
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3498210
> Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>

BUG=b:188011323
TEST=tast run health.DiagnosticsRun.cpu_cache

Change-Id: I313620d99726ed185ba2ec04df4413e43a612670
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3537260
Reviewed-by: Anton Romanov <romanton@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This commit is contained in:
Daniel Verkamp 2022-03-21 22:06:25 +00:00 committed by Commit Bot
parent b65b67d1d9
commit baa34b5be5
1 changed files with 26 additions and 2 deletions
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28
x86_64/src/lib.rs
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@ -199,8 +199,18 @@ const GB: u64 = 1 << 30;
const BOOT_STACK_POINTER: u64 = 0x8000;
// Make sure it align to 256MB for MTRR convenient
const MEM_32BIT_GAP_SIZE: u64 = 1024 * MB;
const START_OF_RAM_32BITS: u64 = 0;
const MEM_32BIT_GAP_SIZE: u64 = if cfg!(feature = "direct") {
// Allow space for identity mapping coreboot memory regions on the host
// which is found at around 7a00_0000 (little bit before 2GB)
//
// TODO(b/188011323): stop hardcoding sizes and addresses here and instead
// determine the memory map from how the VM has been configured via the
// command line.
2560 * MB
} else {
768 * MB
};
const START_OF_RAM_32BITS: u64 = if cfg!(feature = "direct") { 0x1000 } else { 0 };
const FIRST_ADDR_PAST_32BITS: u64 = 1 << 32;
// Reserved memory for nand_bios/LAPIC/IOAPIC/HPET/.....
const RESERVED_MEM_SIZE: u64 = 0x800_0000;
@ -1560,6 +1570,20 @@ mod tests {
assert_eq!(bios_len, regions[1].1);
}
#[test]
#[cfg(feature = "direct")]
fn end_addr_before_32bits() {
// On volteer, type16 (coreboot) region is at 0x00000000769f3000-0x0000000076ffffff.
// On brya, type16 region is at 0x0000000076876000-0x00000000803fffff
let brya_type16_address = 0x7687_6000;
assert!(
END_ADDR_BEFORE_32BITS < brya_type16_address,
"{} < {}",
END_ADDR_BEFORE_32BITS,
brya_type16_address
);
}
#[test]
fn check_32bit_gap_size_alignment() {
// 32bit gap memory is 256 MB aligned to be friendly for MTRR mappings.