From e500f8851c17c6d1d483cecb1467c8886f2e6680 Mon Sep 17 00:00:00 2001 From: Frederick Mayle Date: Fri, 1 Nov 2024 14:15:27 -0700 Subject: [PATCH] aarch64: delete AARCH64_AXI_BASE constant This doesn't seem to correspond to any devices setup by crosvm. We don't support an AXI bus. Searching for 0x40000000 doesn't turn up anything relevant. BUG=b:361390145 Change-Id: Ica4c5bf6ca7b8b417470c37bffd5790776d4086d Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/5984062 Commit-Queue: Frederick Mayle Reviewed-by: Daniel Verkamp --- aarch64/src/lib.rs | 3 +-- devices/src/irqchip/geniezone/mod.rs | 4 +--- devices/src/irqchip/kvm/aarch64.rs | 4 +--- docs/book/src/appendix/memory_layout.md | 2 -- 4 files changed, 3 insertions(+), 10 deletions(-) diff --git a/aarch64/src/lib.rs b/aarch64/src/lib.rs index 2e47537449..0b0ef3c2b0 100644 --- a/aarch64/src/lib.rs +++ b/aarch64/src/lib.rs @@ -104,7 +104,6 @@ const AARCH64_GIC_CPUI_SIZE: u64 = 0x20000; // This indicates the start of DRAM inside the physical address space. const AARCH64_PHYS_MEM_START: u64 = 0x80000000; -const AARCH64_AXI_BASE: u64 = 0x40000000; const AARCH64_PLATFORM_MMIO_SIZE: u64 = 0x800000; const AARCH64_PROTECTED_VM_FW_MAX_SIZE: u64 = 0x400000; @@ -117,7 +116,7 @@ const AARCH64_PVTIME_SIZE: u64 = 64; // These constants indicate the placement of the GIC registers in the physical // address space. -const AARCH64_GIC_DIST_BASE: u64 = AARCH64_AXI_BASE - AARCH64_GIC_DIST_SIZE; +const AARCH64_GIC_DIST_BASE: u64 = 0x40000000 - AARCH64_GIC_DIST_SIZE; const AARCH64_GIC_CPUI_BASE: u64 = AARCH64_GIC_DIST_BASE - AARCH64_GIC_CPUI_SIZE; const AARCH64_GIC_REDIST_SIZE: u64 = 0x20000; diff --git a/devices/src/irqchip/geniezone/mod.rs b/devices/src/irqchip/geniezone/mod.rs index 3904c6bb61..77124a7f79 100644 --- a/devices/src/irqchip/geniezone/mod.rs +++ b/devices/src/irqchip/geniezone/mod.rs @@ -55,7 +55,7 @@ const AARCH64_GIC_DIST_SIZE: u64 = 0x10000; // These constants indicate the placement of the GIC registers in the physical // address space. -const AARCH64_GIC_DIST_BASE: u64 = AARCH64_AXI_BASE - AARCH64_GIC_DIST_SIZE; +const AARCH64_GIC_DIST_BASE: u64 = 0x40000000 - AARCH64_GIC_DIST_SIZE; const AARCH64_GIC_REDIST_SIZE: u64 = 0x20000; // This is the minimum number of SPI interrupts aligned to 32 + 32 for the @@ -64,8 +64,6 @@ const AARCH64_GIC_REDIST_SIZE: u64 = 0x20000; // Number of SPIs (32), which is the NR_IRQS (64) minus the number of PPIs (16) and GSIs (16) pub const AARCH64_GIC_NR_SPIS: u32 = 32; -const AARCH64_AXI_BASE: u64 = 0x40000000; - impl GeniezoneKernelIrqChip { /// Construct a new GzvmKernelIrqchip. pub fn new(vm: GeniezoneVm, num_vcpus: usize) -> Result { diff --git a/devices/src/irqchip/kvm/aarch64.rs b/devices/src/irqchip/kvm/aarch64.rs index 46ff791094..452a140e82 100644 --- a/devices/src/irqchip/kvm/aarch64.rs +++ b/devices/src/irqchip/kvm/aarch64.rs @@ -48,7 +48,7 @@ const AARCH64_GIC_CPUI_SIZE: u64 = 0x20000; // These constants indicate the placement of the GIC registers in the physical // address space. -const AARCH64_GIC_DIST_BASE: u64 = AARCH64_AXI_BASE - AARCH64_GIC_DIST_SIZE; +const AARCH64_GIC_DIST_BASE: u64 = 0x40000000 - AARCH64_GIC_DIST_SIZE; const AARCH64_GIC_CPUI_BASE: u64 = AARCH64_GIC_DIST_BASE - AARCH64_GIC_CPUI_SIZE; const AARCH64_GIC_REDIST_SIZE: u64 = 0x20000; @@ -58,8 +58,6 @@ pub const AARCH64_GIC_NR_IRQS: u32 = 64; // Number of SPIs (32), which is the NR_IRQS (64) minus the number of PPIs (16) and GSIs (16) pub const AARCH64_GIC_NR_SPIS: u32 = 32; -const AARCH64_AXI_BASE: u64 = 0x40000000; - impl KvmKernelIrqChip { /// Construct a new KvmKernelIrqchip. pub fn new(vm: KvmVm, num_vcpus: usize) -> Result { diff --git a/docs/book/src/appendix/memory_layout.md b/docs/book/src/appendix/memory_layout.md index 14d0f92a06..a870614a6c 100644 --- a/docs/book/src/appendix/memory_layout.md +++ b/docs/book/src/appendix/memory_layout.md @@ -68,7 +68,6 @@ These apply for all boot modes. | [`AARCH64_MMIO_BASE`] | `200_0000` | `400_0000` | 32 MiB | Low MMIO allocation area | | [`AARCH64_GIC_CPUI_BASE`] | `3ffd_0000` | `3fff_0000` | 128 KiB | vGIC | | [`AARCH64_GIC_DIST_BASE`] | `3fff_0000` | `4000_0000` | 64 KiB | vGIC | -| [`AARCH64_AXI_BASE`] | `4000_0000` | | | Seemingly unused? Is this hard-coded somewhere in the kernel? | | [`AARCH64_PROTECTED_VM_FW_START`] | `7fc0_0000` | `8000_0000` | 4 MiB | pVM firmware (if running a protected VM) | | [`AARCH64_PHYS_MEM_START`] | `8000_0000` | | --mem size | RAM (starts at IPA = 2 GiB) | | [`plat_mmio_base`] | after RAM | +0x800000 | 8 MiB | Platform device MMIO region | @@ -111,7 +110,6 @@ with a 16 MiB alignment. [`aarch64_mmio_base`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=196?q=AARCH64_MMIO_BASE [`aarch64_gic_cpui_base`]: https://crsrc.org/o/src/platform/crosvm/devices/src/irqchip/kvm/aarch64.rs;l=106?q=AARCH64_GIC_CPUI_BASE [`aarch64_gic_dist_base`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=105?q=AARCH64_GIC_DIST_BASE -[`aarch64_axi_base`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=86?q=AARCH64_AXI_BASE [`aarch64_pvtime_ipa_start`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=100?q=AARCH64_PVTIME_IPA_START [`aarch64_protected_vm_fw_start`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=96?q=AARCH64_PROTECTED_VM_FW_START [`aarch64_phys_mem_start`]: https://crsrc.org/o/src/platform/crosvm/aarch64/src/lib.rs;l=85?q=AARCH64_PHYS_MEM_START