The pci_irqs list contains an entry for each PCI device, but IRQ numbers
may be reused, so the MADT would contain duplicate interrupt override
entries in this case. This doesn't cause a problem in practice (the
duplicates are all identical and the guest kernel does not complain),
but it makes sense to remove the duplicates and only add a single
IOAPIC interrupt override entry per unique IRQ number.
BUG=b:207551552
TEST=x86_64 guest kernel only has 4 INT_SRC_OVR logs in dmesg
Change-Id: Iba4c57ca93d4be6c21e087b2f3f416fe022e8d35
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315408
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Basic functionality works with a purely ACPI-based boot (no MPTable),
but something is still missing in the ACPI tables for describing the
full interrupt routing configuration. The guest kernel complains:
virtio-pci 0000:00:01.0: can't derive routing for PCI INT A
virtio-pci 0000:00:01.0: PCI INT A: no GSI
Restore the acpi=noirq option for now until we fill out the ACPI IRQ
descriptors correctly; this was a cleanup only and not required to fix a
bug.
This reverts commit cb464a7c08.
BUG=None
TEST=Boot Crostini; no interrupt routing failures in dmesg
Change-Id: Ib73c5749b48134124b3ebcb472706f087e8a85a2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315226
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Now that we provide a correct MADT ("APIC" table ID), there is no need
to override the kernel ACPI option that made it ignore these tables.
BUG=None
TEST=Boot crosvm with setup_mptable() call removed, ACPI only
Change-Id: I9f4589738462c5693f151f60180c79d054a9084d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313841
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
KVM's irqchip emulation provides the traditional PC-style pair of 8259
PICs, so report this by setting the appropriate flag in the MADT (APIC)
table.
BUG=b:207551552
TEST=Boot crosvm with setup_mptable() call removed
Change-Id: Ib5adf7ac717156deb3cd19d74873c9745ae826ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313840
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Add interrupt redirection entries to MADT so that the legacy pin-based
interrupts are correctly reported as level triggered. This matches the
entries in the existing MPTable, but those are not availble when booting
with OVMF, which only provides ACPI tables.
This fixes an issue where USB device sharing was failing in some cases
when booted with ACPI only, since our xhci controller emulation only
supports pin-based interrupts (not MSI-X) and would not work correctly
when the guest incorrectly treated its IRQ as edge triggered.
BUG=b:207551552
TEST=Start crosvm with setup_mptable() call removed
TEST=Share USB device when booted with ACPI via OVMF
Change-Id: Id3e4ff5ba9587aadbeadbcc8eceaa771c4c2d5df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3312577
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
This function doesn't need to consume the pci_irqs vector, just iterate
over it.
BUG=None
TEST=tools/presubmit
Change-Id: Ibb66fa6ab8c45f58eeb89b976bcfc57e00d718a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313996
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
PcieRootPort implement hotplug_bus trait, it should be added into
RunnableLinuxVm->hotplug_bus, so create pcie root port when
RunnableLinuxVm->hotplug_bus is ready.
Many hotplug bus may exist, when a hotplug device is added, is_match()
should be called on each hotplug bus before attach that device to
the bus.
BUG=b:185084350
TEST=Boot a vm with passthrough device and check its function
Change-Id: I89dbc091f336b3f9d0435b52963f7cf62d408a67
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2955570
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
There were not too many cases here. This fixes:
- comparison_chain
- wrong_self_convention
- upper_case_acronyms
- from_over_into
- let-and-return
The collapsible_if check is moved to the permanently
allowed checks. The cases we do have improve
readability or semantics.
BUG=chromium:908640
TEST=Kokoro
Change-Id: I6e905d08e2a87aa0862d4d1cf5ff57b60e95fa7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3278776
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Use the anyhow crate to provide ad-hoc errors with context. This removes
the large, manually-updated enum, which we never use programmatically
anyway (error messages are printed in human-readable form and otherwise
not matched against).
BUG=b:190433480
TEST=cargo build
TEST=./test_all
Change-Id: Ia7b90b33774d4031054b346d650861d3105044ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3105436
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Original reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Fixed by clamping the maximum physical address to 64 TiB, which is the
largest physical address supported by x86-64 Linux with only 4-level
page tables enabled.
In addition, the high MMIO region size calculation has been split into a
separate function, get_high_mmio_size(), and an off-by-one error in the
size calculation was fixed.
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This is a reland of https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
BUG=b:199442120
BUG=b:185084350
TEST=Crostini starts on grunt (AMD device)
TEST=crosvm run --pmem-device rootfs -p 'root=/dev/pmem0' kernel
Change-Id: I7c93f7132dbfbc3f38ecbfa0504b59214a1eb6bf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3251788
Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This change contains the results of running
./tools/contib/cargo_refactor.py
This will break the next uprev, and needs to be synchronizized
with the corresponding ebuild changes in https://crrev.com/c/3248925
BUG=b:195126527
TEST=./tools/run_tests
Change-Id: Ied15a1841887bb8f59fba65b912b81acf69beb73
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248129
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This reverts commit 9557588786.
Reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Bug: b:199442120
Bug: b:185084350
Change-Id: Ida1369bf0b70782633b1073ceef50e1bab108f55
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248906
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Rust bindgen now supports --allowlist and --blocklist option names as of
https://github.com/rust-lang/rust-bindgen/pull/1990 - use them in the
various bindgen invocations in scripts and comments.
BUG=b:178821708
TEST=../dev/contrib/search_blocked_words.sh unblocked_terms.txt
Change-Id: I9797f049999a01ab2c41617823463236b4d03cbb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3243012
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Some devices like virtio-pmem, intel host bridge need private mmio, these private
mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
then resource conflict happens.
This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
is large enough and OS allocates pci mmio from low to high. So these non pci bar
mmio won't conflict with pci bar.
BUG=b:199442120
BUG=b:185084350
TEST=crosvm run --pmem-device xxxx
Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present the Guest generates its own CPU topology. To mitigate
cross-hyperthread speculative execution side channel attacks, allow
Guest to use mirror CPU topology of Host is needed for future scheduling
optimization.
Add a config option "--host-cpu-topology" to ask the vCPU number to be
identical to physical CPUs, and make the vCPU has the same APIC ID in
MADT and CPUID as the corresponding physical CPU. The same APIC ID can
ensure the same topology.
"--host-cpu-topology" requires vCPU number must equal to pCPU number,
and it has the default vCPU number setting, which equals to pCPU number.
"--host-cpu-topology" also defaultly sets CPU affinity for each vCPU to
the pCPU which has the same processor ID, like 1=1:2=2:3=3:4=4, so that
the vCPU and its corresponding pCPU will have the same processor ID and
the same APIC ID. User can't set CPU affinity if "--host-cpu-topology"
was set.
BUG=b:197875305
TEST=Set "--host-cpu-topology" option and check Guest's /proc/cpuinfo,
lscpu, CPUID for different vCPU
Change-Id: Ibc4eb10649e89f43b81bde6d46d6e0e6c7234324
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217035
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
At present the Guest use the cpu id (enum number) as the APIC ID in vCPU
CPUID and set the different topology with pCPU.
To support the feature vCPU has the same topology as pCPU, vCPU need the
same APIC ID as pCPU. So let vCPU can use the APIC ID from pCPU in
vCPU's CPUID and keep pCPU's topology related information (include CPU
count and topology mask) unchanged.
Now this change is a preliminary preparation and doesn't work.
Additional feature options and corresponding CPU number and CPU affinity
settings are still required.
BUG=b:197875305
TEST=cargo build
TEST=./test_all
Change-Id: I04150ac6c35534d0ff56667b01f448da2ca9f9fc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217034
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
At present the Guest use the cpu id (enum number) as the APIC ID in
Guest MADT.
To support the feature vCPU has the same topology as pCPU, vCPU need
the same APIC ID as pCPU. So let Guest MADT can use the APIC ID from
Host is needed.
Now this change is a preliminary preparation and doesn't work. The APIC
ID related changes for vCPU CPUID are still required.
BUG=b:197875305
TEST=cargo build
TEST=./test_all
Change-Id: I0e7dfba8cd57fefd85b7d7e37de3bb9935ff19ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217033
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
With vfio pci device hotplug, bus->devices will be inserted and removed at
runtime in different vcpu threads, so mutex should be used to protect it.
Both each vcpu thread and pci_root share mmio_bus and io_bus, so use Arc
for mmio_bus and io_bus. But pci_root is inserted into io_bus for pci cfg io,
in order to resolve reference loop and memory leak, weak is used for
pci_root.mmio_bus and pci_root.io_bus.
BUG=b:174705596
TEST=boot a vm and check its function
Change-Id: I7b3e63db76a90bc3873619b4d80a66db741ce78f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184724
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This was an oversight from the previous commit to pass the kernel
command line to a bios.
BUG=b:200208446
TEST=Observe pstore working across reboots
Change-Id: Ie93cc3399000a83099d396f4dde1da9d835704be
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3197732
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Noah Gold <nkgold@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Auto-Submit: Tom Cherry <tomcherry@google.com>
Before we call build_vm we are creating devices and there is no reason
to assume those have to be PCI only. In preparation for VFIO platform
device support, add super trait which allows to pass generic device
structure around and still be able get back to our original type.
BUG=b:185504618
TEST=manatee PCI device passthrough boots/works
Change-Id: I500f44af430f5f06299f20fc4ca17ca008a7e0c5
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2961210
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Nowicki <tnowicki@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This enables the bios to read kernel command line parameters
from crosvm and pass them to the kernel that it loads.
BUG=b:195323844
TEST=pass --params through uboot to Linux
Change-Id: I306bb16421393583edc8b0dbdb3198a5b3cc0377
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3140277
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tom Cherry <tomcherry@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Replace the uses of read_struct() and read_struct_slice() with the
safe DataInit::from_reader() implementation.
BUG=b:197263364
TEST=./test_all
TEST=Boot bzImage kernel
TEST=Boot raw ELF kernel extracted with extract_vmlinux
Change-Id: I80f98243bfb58a7ae93e1686bc4d92b0cd485cda
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108249
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Tree-wide cleanup of new clippy warning in Rust 1.54 that warns about
needless borrows:
error: this expression borrows a reference (`&...`) that is
immediately dereferenced by the compiler
https://rust-lang.github.io/rust-clippy/master/index.html#needless_borrow
BUG=b:197251702
TEST=bin/clippy # with rust-toolchain = 1.54.0
Change-Id: Ib702ec524d4623d264a00ec11dbc2150c411a67b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108321
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Allen Webb <allenwebb@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Add necessary kernel cmdlines for aarch64.
Adjust PCI address to make room for ramoops on aarch64.
Move the code from x86_64 to common places.
BUG=b:153934386
TEST=vm_pstore_dump
Change-Id: I8f92a7fd04a49afd7e8be9e7cf1901ef70b88d65
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3103131
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Kansho Nishida <kansho@chromium.org>
Commit-Queue: Ryo Hashimoto <hashimoto@chromium.org>
Device implement HotPlugBus trait could notify hotplug event into
guest, and such device should be added into RunnableLinuxVm, so it
could be used at device plug in and plug out.
BUG=b:185084350
TEST=Boot a guest with and without passthrough device
Change-Id: I9497f61312582483090ff708d0f37b97d7303811
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2954673
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
When a vfio pci device is added through hotplug in, it should be configured
at runtime and added into pci_root->devices tree, so pci_root is added
into linux.
BUG=b:185084350
TEST=Boot a guest with and without passthrough device
Change-Id: Ibcb5f4a849134f64fbceeac645bebd80d6ca72d5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2954672
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Move the definitions of SerialHardware, SerialParameters and SerialType
to the devices crate so that they'll be available for code in the
devices crate as well.
BUG=b:195495971
TEST=cargo test
Change-Id: Ieb711bdb18a8afdb28cac262a3355739604d4607
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3096439
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
BUG=b:191784608
TEST=Build and run atest in Android tree
Cq-Depend: chromium:3073700
Change-Id: I5fcfa166caf8c5a5f759a8f62ef78a293db95f1a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3071900
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andrew Walbran <qwandor@google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
This flag is intended to be used to delay making a VM's RT VCPUs
RT until "make_rt" is called, in order to avoid boot time
regressions with RT.
BUG=b:142777321
TEST="grep policy /proc/<pid of rt vcpu>/sched" to make sure RT vcpu
isn't RT until "make_rt".
Change-Id: I1b9132e11f0acc626434c60cecc2f4afe350961a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2703224
Auto-Submit: Suleiman Souhlal <suleiman@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Suleiman Souhlal <suleiman@chromium.org>
The devices to be notified on resume are unrelated to the functionality
of Bus, which is looking up devices in an address space. Additionally,
each Bus instance had its own list of devices to notify, although in
practice, only the one in the I/O bus was used.
Move the resume_notify_devices list into RunnableLinuxVm instead.
BUG=None
TEST=Boot Crostini on x86 and arm
Change-Id: I72c629c6d6589c4a9350831c8a076c5c0c9f9aeb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3043489
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Supply the OS with basic PCI hostbridge information (PIO region, MMIO
region, etc) using Device (_SB.PCI0) in DSDT. Without this info the
Linux kernel behaves erroneously in iova_reserve_pci_windows().
Output from the Linux kernel, w/o _SB.PCI0:
pci_bus 0000:00: root bus resource [mem 0x00000000-0x7fffffffff]
Since DSDT contains PCI hostbridge information, ACPI is always required.
Use "acpi=noirq" in cmdline when DSDT/MADT is not provided by the user.
The Linux kernel refers to PCI configuration space for interrupt
routing.
BUG=b:181736020
TEST=boot Linux kernel and check dmesg
Change-Id: Id328a958fb770e087788e71fe480839eab4f40c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2846422
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: David Stevens <stevensd@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
In VT-d, the IOMMU hardware can translate guest physical address that
is no more than MGAW (Maximum Guest Address Width) which is reported
from the VT-d Capability register.
We pass this information to the guest IOMMU front driver so that it
can allocate appropriate IOVA.
VT-d indicates that "implementations must support MGAW at least equal
to the physical addressability (host address width) of the platform".
Thus we take the Physical Address Bits that is reported by
CPUID.80000008H as the minimum MGAW.
BUG=b:181736020
TEST=--vfio=/sys/bus/pci/devices/0000:00:14.0,iommu=on
Change-Id: I26a421ea2e7dd893d413d63ab313721cfdf0b5c1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2757278
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: David Stevens <stevensd@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: David Stevens <stevensd@chromium.org>
Most of the MADT describes hardware that isn't passed through to the
guest. Instead of passing that information to the guest, use a MADT
generated by crosvm. However, we do want to pass through the irq
override structures, so append those to the generated MADT.
BUG=none
TEST=boot kindred and observe 2 cores in the CrOS guest
Change-Id: Ia7279578f2eab6be1092817e3c2700905c10dd05
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2908281
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: David Stevens <stevensd@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Fixes clippy warnings like:
using `clone` on type `...` which implements the `Copy` trait
and
redundant clone
note: this value is dropped without further use
BUG=None
TEST=bin/clippy
TEST=cargo test -p devices
Change-Id: I8c13b79b54265e5527cadcb8a2e9f54419044bcf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2885781
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
SMI Interface is not supported by crosvm. Clear FADT.SMI_COMMAND field
to disable ACPI enable/disable transitions.
BUG=b:145604457
TEST=Boot system with user provided ACPI tables.
Change-Id: I17daafc4b2ffded5ba8235ad19e24aa67ad5c8a6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2893368
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
This will be used to dynamically add and remove bus ranges when the PCI
command register is updated to enable/disable memory and IO decode.
BUG=b:174705596
TEST=cargo test -p devices
Change-Id: I6bb175e0628bf598d049562700e2f55a2a62df59
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2689081
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
These parameters multiplied the number of type arguments to build_vm
unnecessarily and complicated the thread of execution in the programmers
head. Closures also complicate the borrow rules, making things much
harder to change.
This change uses the results of the closures (e.g. PCI devices, IRQ
chips) as parameters instead. The rest of this change follows naturally
from pulling on that thread until tests pass.
As a result of the removal of several type arguments, the code size was
reduced by ~100KiB on a 5MiB build.
BUG=b:185170486
TEST=./test_all
Change-Id: I6bcc5eb1b1f3031d4328bb4a81ddef618d04767b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2829136
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Zach Reizner <zachr@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
User provided DSDT/MADT/FADT tables will have precedence
over crosvm generated data, with crosvm only overriding
critical FADT fields to match ACPI tables placement.
Also, this patch adds mandataory empty FACS structure.
BUG=None
TEST=run guest with set of ACPI tables provided and verify content.
Change-Id: I3f3ff2170c08b3f570ff863ecc45c5bf203eb940
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2841754
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This requires exporting the memory layout from the arch crates, but it
does simplify the bloated build_vm interface a bit. It also will allow
for more fine-grained control the backing memory of GuestMemory.
TEST=test_all
BUG=b:183988204
Change-Id: Ie76755198d2fdc2a41bd538650939d6550686b88
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2809434
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Zach Reizner <zachr@chromium.org>
Some judgement calls were made about unnecessary wrapping. Usually they
would get resolved by removing the wrapping or returning a convenient
error, but the ones that returned results for consistency with other
functions were added to the allow list.
The error handling in the usb code had a lot of unit error types which
is now a clippy lint. This was resolved by either removing the result
entirely or returning a convenient error.
The field_reassign_with_default lint is faulty and was added to the list
of supressions. This affected virtio-wayland code.
BUG=b:179277332
TEST=cargo clippy with rustc 1.50+
Change-Id: Ie812cdeaf7c42f4f2b47b1dc87f05a7c87a60f8f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2757510
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Auto-Submit: Zach Reizner <zachr@chromium.org>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
More recent Intel IO-APICs can support more than 24 interrupt
lines. This change enables variable size of IO-APIC lines for
user level IO-APIC emulation code (split-irqchip).
Reported version and supported IO-APIC registes matching ICH10
implementation of IO-APIC device.
BUG=b:181795297
TEST=boot and allocate irq from upper range.
Change-Id: I56480befb39c4c268266f04e4a93105402248772
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2733579
Tested-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Ovmf goes through all entries in smbios table, without end entry,
assert() failure occurs.
BUG=b:179053182
TEST='crosvm run -bios OVMF.fd' and boot OVMF into efi shell
Change-Id: I0068133c75583dc4a3477d01a58f0ee8775b509e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2741918
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This removes some unsafe code, improving the interface so that it cannot
be misused (e.g. previously, different Vec<u8> instances could be passed
to fdt functions that did not validate the contents).
The new implementation also adds some extra error checking to catch
invalid string values in all API entry points that accept strings, as
well as out-of-order node nesting that would result in DTB data that did
not conform to the spec.
BUG=b:175729255
TEST=cargo test -p arch
TEST=Boot Crostini on kevin (arm)
TEST=diff old and new dts from `dtc -I fs -O dts /proc/device-tree`
Change-Id: I567d562ed1b447aa0d282b68c71758edea13ffc0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2713569
Reviewed-by: Zach Reizner <zachr@chromium.org>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
- Add an address space region for the protected KVM firmware.
- Query firmware size, mmap something that size and create a memslot.
BUG=b:163789172
TEST=cargo test
Change-Id: I054cf5d763c980d073c17bce70e85a781816b64d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2623942
Auto-Submit: Andrew Walbran <qwandor@google.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Walbran <qwandor@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
A BIOS can be larger or smaller than 1 MB; as long as the image is
placed so the reset vector lines up in the correct place at the end of
the 32-bit address space, everything should work.
BUG=b:179053182
TEST=`crosvm run --bios OVMF.fd` and observe debug messages
Change-Id: Ibafd9bb5ee4fd4b0ff2c28c38f022ff3b36dd95d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2651288
Reviewed-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
rutabaga_gralloc is a cross-platform, Rust-based buffer
manager.
The rationale for this change is:
1) For the {cross-domain, wayland} context type, we need to
have a good story for the crucial "wl-dmabuf" feature. As
minigbm has been thoroughly tested on ChromeOS and currently
powers the "wl-dmabuf" feature, it only makes sense for us to
have a path to minigbm for the cross-domain prototype. This
will be used by Sommelier.
2) While minigbm allocation works well on Chromebooks, it is
not sufficient for cross-platform purposes. For their Virtual
Graphics Interface (VGI) initiative, Android graphics
virtualization experts have expressed their desire for a Vulkan
based allocator. This will to go alongside cros_gralloc in
minigbm, which is considered by many to be the ""world's
premiere gralloc implementation".
3) Android graphics virtualization experts have expressed their
desire for vkMapMemory(..) to be used when crosvm is in
multi-process mode. Currently, only dma-buf mmap() is supported
for zero-copy blobs in multi-process mode. dma-buf mmap() is not
guaranteed to work on Nvidia (a "must have" for Cuttlefish) or
any other driver for that matter (we *make* it work for ChromeOS).
Possibly only solution: vkMapMemory ;-)
With these goals in mind, here's a summary of the revelant changes:
* Renamed the {gpu_allocator.rs, GpuMemoryAllocator trait} to be
{gralloc.rs, Gralloc trait}.
* Moved all GPU allocation out of the resources crate and into
the rutabaga_gfx crate. This will allow the resources crate to
be focused on managing resources for virtual machines.
* Moved the gpu_buffer crate into the gralloc module in the
rutabaga_gfx crate. The same functionality is now under
"minigbm.rs", "minigbm_bindings.rs" and "rendernode.rs"
* Added an optional dependency on vulkano.rs. vulkano.rs is a safe
Rust wrapper around the Vulkan api [a]. It's emphasis on type
safety makes a good fit for crosvm, though there are other high
quality crates out there (gfx-rs, ash.rs). Though development
has slowed down, it should satisfy goals (2) and (3) quite easily.
* Added a system_gralloc implementation based on memfd. This can be
used when minigbm or Vulkano features are not used, to replicate the
highly useful "wl-shm" feature in Sommelier. Astute observers will
note this can also enable seamless Wayland windowing without GPU
features for Android too. Some minor changes to the base crate were
needed.
* Cut down on the amount of DrmFormats to the subset needed by
Sommelier and cros_gralloc.
* Moved checked arithmetic into it's own file.
* Internally renamed to "wl-dmabuf" feature to be the "minigbm"
feature. This is because "wl-dmabuf" has a dependency on minigbm.
* Small rutabaga_gfx cleanups
[a] https://github.com/vulkano-rs/vulkano/blob/master/DESIGN.md
BUG=b:146066070, b:173630595, b:150239451
TEST=launch virtual machine with 2D mode
TEST=launch virtual machine with 3D mode
TEST=run sommelier with "wl-dmabuf" and "wl-shm"
Change-Id: I693a39cef64cd98e56d843d3c60caa7983d4d6e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2626487
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Commit-Queue: Gurchetan Singh <gurchetansingh@chromium.org>
This test was useful for debugging issues with the hypervisor
abstraction layer while it was in development. It's similar to some of
the kvm integration tests, but runs the x86_64 setup functions. It has
some commented out lines for having this test load a real kernel and/or
ramdisk, which can also be useful for debugging boot problems.
RESTRICT_AUTOMERGE
BUG=b:175025264
TEST=cargo test -p x86_64
Change-Id: If5b89fe48d34db50fb962382032881e4e588db6e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2579896
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
When no_smt isn't set, guest works with hyperthread enabled, but crosvm
doesn't emulate processor topology cpuid at this case, so the output of
guest /proc/cpuinfo and lscpu is inconsitent, and guest cpuid is wrong.
This commit adds such support. If vcpu_num is >1 and is even, threads
per core is 2 and cores_num is vcpu_num/2. If vcpu_num is >1 and is odd,
threads per core is vcpu_num and cores_num is 1.
BUG=None
TEST=Check guest /proc/cpuinfo, lscpu, cpuid at different vcpu number
Change-Id: I8d9aaeac3fc911ee91bf2eb0586e457aac27a185
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2548450
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Allow devices to be added to a Bus without a mutex. If a device
implements BusDeviceSync and is inserted into the Bus via the new
insert_sync function, the Bus will not lock the device before write and
read operations. This feature will allow IrqChip implementations to use
the mmio bus for APIC mmio, and allow each vcpu to write to their
respective APICs simultaneously.
This also changes the BusDevice trait so read and write functions take a
new BusAccessInfo struct. The BusAccessInfo conveys the full address of
the read/write operation, the offset of the address relative to the
device start address, and an id that in practice will hold the vcpu id
for the vcpu thread perforing the read/write.
As a result, inserts into the Bus are no longer distinguished between
full_addr and non full_addr inserts. Instead, each device's BusDevice
implementation must decide whether they use the absolute read/write
address or the relative read/write offset.
BUG=chromium:1077058
TEST=ran build_test
TEST=ran simple debian image
Change-Id: I9125aaa69869c1004b6c6a099b50f5c58038d4ab
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2514662
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Add methods to the IrqChip trait to block in userspace on halted vcpus.
Add IrqChip::check_capability, used for cpuid setup.
Move interrupt injection logic from linux.rs to a new
IrqChip::inject_interrupts method, which replaces interrupt_requested
and get_external_interrupt.
These changes are to support setup, run loop, and injection in the
userspace irqchip.
BUG=chromium:1077058
TEST=boots with KVM kernel irqchip, KVM split irqchip
Change-Id: I8f46b5edf36acc485b5f76e7aed3e71c3b984c0e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2419674
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
The S5 capability allows the VM to be powered off when user execute
'poweroff' command. This is done by trigger the exit event through
the ACPI PM1 control so that crosvm can shutdown the VM in the end.
BUG=None
TEST=boot a VM and then run 'poweroff' command from VM's shell. The
VM can exit.
Change-Id: Iaad5615fd72550568362090c3b876202055cc25a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2534098
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Add a new command "battery" which is used to modify the virtual
battery/ac status.
When there is goldfish battery device model created, the command
is able to sent to the goldfish battery monitoring thread. If no,
the command won't be sent.
The supported commands are:
1. crosvm battery goldfish status <status string> crosvm.sock
2. crosvm battery goldfish health <health string> crosvm.sock
3. crosvm battery goldfish present <number> crosvm.sock
4. crosvm battery goldfish capacity <number> crosvm.sock
5. crosvm battery goldfish aconline <number> crosvm.sock
"goldfish" is the battery identifier to specify which virtual battery
is going to be modified by this command in case there are multiple
virtual batteries in the guest in future. Right now only one goldfish
battery is supported.
BUG=chromium:1050432
BUG=b:137890633
TEST=create VM with parameter "--battery" or "--battery=type=goldfish"
and boot linux guest with goldfish_battery driver enabled. From host
side, execute command "#crosvm battery goldfish status discharging
crosvm.sock" can make the guest receive an interrupt, and the status
sysfs is changed to "Discharging". Also tested the other commands
as well.
TEST=modified values are visible in ARCVM and interrupts are triggered
Change-Id: I82177811a6f2b1960f7895522760ff3b8143163f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2119574
Tested-by: Alex Lau <alexlau@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Alex Lau <alexlau@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
The goldfish battery irq will be used to notify the guest driver that
battery/ac status changed. And the status changing will be done through
external crosvm commands. So the irq injection needs to be done in a
seperate thread which can receive these commands.
BUG=chromium:1050432
BUG=b:137890633
TEST=create VM with parameter "--battery" or "--battery=type=goldfish"
and boot linux guest with goldfish_battery driver enabled. The sysfs
created by the goldfish_battery driver have no issue observed.
TEST=goldfish_battery driver is loaded on ARCVM and interrupts are enabled
Change-Id: Icc902dd8c00bdcf6cb271b20d928a4081533dde6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2119573
Commit-Queue: Alex Lau <alexlau@chromium.org>
Tested-by: Alex Lau <alexlau@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Add a flag '--gdb <port>' to provide GDB remote protocol interface so
a developer can attach GDB to the guest kernel.
In this CL, we support read/write operations for registers and memories.
BUG=chromium:1141812
TEST=Attach gdb and see register values on workstation and intel DUT
Change-Id: Ia07763870d94e87867f6df43f039196aa703ee59
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2440221
Commit-Queue: Keiichi Watanabe <keiichiw@chromium.org>
Tested-by: Keiichi Watanabe <keiichiw@chromium.org>
Auto-Submit: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Create goldfish battery device model for guest. Provide the
minimal properties and basic accessing for the golfish_battery
driver in the guest.
BUG=chromium:1050432
BUG=b:137890633
TEST=create VM with parameter "--battery" or "--battery=type=
goldfish" and boot linux guest with goldfish_battery driver
enabled. The goldfish_battery driver is loaded successfully.
The /sys/class/power_supply/battery and
/sys/class/power_supply/ac are created successfully.
TEST=cargo test -p crosvm
TEST=goldfish_battery driver is loaded on ARCVM after crrev.com/c/2519336
Change-Id: Iaafa09e3d7e5664d3db8b7df5295f077ec3f6da9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2119572
Commit-Queue: Alex Lau <alexlau@chromium.org>
Tested-by: Alex Lau <alexlau@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Virtio 1.1 introduces the VIRTIO_F_ACCESS_PLATFORM reserved feature bit,
which allows the guest operating system to discover that a virtio device
has limited access to memory. In the case of Linux, this forces the use
of the DMA API for virtio transfers, which in turn can bounce data
through a shared window that is negotiated between the guest and the
hypervisor.
Advertise the VIRTIO_F_ACCESS_PLATFORM reserved feature bit when crosvm
is running with the '--protected-vm' option.
BUG=None
TEST=./build_test
Change-Id: I78e8d9e78999790059639b64611b8081c39d24ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2453560
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
This allows code to create references to traits such as `&dyn Vcpu` for
`&dyn IrqChip`. This also allows keeping such traits inside of opaque
`Box` like wrappers.
To achieve this, trait methods referencing `Self` have an additonal
`where` clause that restricts them to sized types. Associated types are
removed and replaced with their trait equivalents (as parameters) or an
opaque Box (as return values).
To work around certain cases where a concrete type is needed, such as
for KVM based `IrqChip` impls, the `downcast_rs` trait is used to allow
`dynamic_cast` style casting.
The binary size impact of this change is small. For comparison, here is
the size change with this commit:
armv7a -0.49% (-9 kiB)
aarch64 -0.17% (-3 kiB)
x86_64 +1.77% (+40 KiB)
BUG=None
TEST=build_test
Cq-Depend: chromium:2466660
Change-Id: I1a408734832d2971ea2979c1bc64b2ffe051b02d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2439298
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Zach Reizner <zachr@chromium.org>
When set, VCPUs aren't presented to the guest as hyperthreads,
on Intel.
Instead, present them as different, non-hyperthreaded cores on
the same package. Presenting them as hyperthreads might make the
guest scheduler migrate tasks between VCPUs more aggressively,
which can be expensive in a VM.
AMD will need a different CL.
BUG=b:169828263
TEST="cat /proc/sys/kernel/sched_domain/cpu0/domain0/name" in
the guest returns "MC" instead of "SMT" when starting crosvm
with --no-smt.
Change-Id: Ifdb4d54a3d7d83c5620fa768ce88ba1a0d85ee50
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2460534
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Suleiman Souhlal <suleiman@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Suleiman Souhlal <suleiman@chromium.org>
Note the CL size is large entirely due to the rename,
the changes are mostly negligible.
Also making a few small additional changes in sys_util
areas that don't need much attention in base. This includes
typedefing and adding specific imports for areas that don't
require significant interface changes.
BUG=b:162363783
TEST=./build_test
Change-Id: I4a2c9c4cdce7565806ed338e241c6b8c82c855c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2415180
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Michael Hoyle <mikehoyle@google.com>
This is very largely boilerplate, but changes some interfaces
to accept different parameters, esp using Descriptor.
BUG=b:162363783
TEST=./build_test
Change-Id: I81b513c0de9448c2de505fe5d3a61a29f4eccb78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2342591
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Michael Hoyle <mikehoyle@google.com>
This leaf is used to identify the APIC ID on Intel systems.
Fixes guest kernel warnings of this type:
[Firmware Bug]: CPU1: APIC id mismatch. Firmware: 1 APIC: 11
BUG=b:167714813
TEST=Boot Linux guest kernel; check dmesg
Change-Id: Icc3d32f5a382704c28ecc174b98c982c574bd2b0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2402154
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
The existing mem_below_4g/mem_above_4g calculations did not match the
actual layout used when populating guest memory. Rather than
duplicating the logic in setup_io_bus to calculate the values reported
in CMOS, just reuse the arch_memory_regions function and count the bytes
in the regions below and above the 4G boundary.
BUG=b:168740534
BUG=b:168628037
TEST=Verify u-boot reports 4 GiB with crosvm --mem=4096
Change-Id: I32a70f19848595eaefd2e31c9f31a260d6ce4453
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2422129
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
When the RAM size is specified to be exactly 3328 MiB (4096 - 768),
there is no memory after the gap; however, the arch_memory_regions code
was adding a zero-sized region to the list of guest memory areas to be
mapped.
This would result in a mmap syscall failure at startup:
[ERROR:src/main.rs:1590] The architecture failed to build the vm:
failed to set up guest memory: failed to map guest memory: mmap system
call failed: Invalid argument (os error 22)
Fix the off-by-one error when checking whether the address of the end of
guest memory is within 4 GB so that the > 4GB branch is not taken with
mem=3328.
BUG=chromium:1129547
TEST=crosvm run --mem=3328 vm_kernel
TEST=cargo test -p x86_64
Change-Id: I66cd66c98d690b42b2e1d97312528bb0d4830e76
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2417004
Reviewed-by: Ram Muthiah <rammuthiah@google.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Add an option to set some vcpus as real time. With a cooperative guest,
this allows for getting real time behavior for a subset of guest
threads. The guest will use cpusets to ensure that only real time tasks
are run on the real-time CPU, and that vcpu thread is real-time on the
host leading to behavior close to host real-time threads.
BUG=b:142777321
TEST=crosvm --rt-cpus 1 [OPTION]...
ps -AT -eo comm,sched,rtprio | grep crosvm_vcpu
then check the sched policy of vcpu1 is 2 (SCHED_RR)
Change-Id: Ic8e7a6840bdbce2c90e518458f6d0c50a65ca3f2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2152167
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Suleiman Souhlal <suleiman@chromium.org>
Tested-by: Kansho Nishida <kansho@chromium.org>
Commit-Queue: Kansho Nishida <kansho@chromium.org>
Calls to the kvm crate have been replaced by calls to hypervisor and
devices::irqchip. Plugin is unchanged and still KVM-specific.
x86 creates and configures vcpus on the vcpu thread instead of the main
thread.
Code that still depends on kvm or kvm_sys:
- crosvm_plugin, plugin, and protos use kvm and kvm_sys if built with
the plugin feature
- devices::VfioGroup does a kvm_sys ioctl
- devices::irqchip and hypervisor use kvm_sys. hypervisor uses
kvm::Cap and kvm::CpuId internally for now.
BUG=chromium:1077058
TEST=runs es2gears_wayland on kukui
TEST=runs evince on amd64-generic with kernel and split irqchip
TEST=build_test excluding tpm2
TEST=cargo check --features plugin
Change-Id: I0068e34da6a5ff0079b1237be1958933bf12ffe4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2307711
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Steven Richman <srichman@google.com>
The emulated CMOS RTC device always returns the hour field in 24-hour
format; initialize the Status Register B bit that indicates this to the
guest.
This also lets Linux register the CMOS RTC as an rtc-class device. It
was previously ignoring it since it was assuming the device was in
12-hour mode.
Also bump the minimum IRQ for the system allocator up to 9 to avoid
sharing IRQ 8, which becomes an issue once Linux tries to enable the RTC
device:
snd_intel8x0 0000:00:0b.0: PCI->APIC IRQ transform: INT C -> IRQ 8
genirq: Flags mismatch irq 8. 00000080 (snd_intel8x0) vs. 00000000 (rtc0)
snd_intel8x0 0000:00:0b.0: unable to grab IRQ 8
snd_intel8x0: probe of 0000:00:0b.0 failed with error -16
On x86_64, only 4 device IRQs are used (for PCI pin interrupts), so this
does not reduce the number of available IRQs for devices. Most PCI
devices in crosvm also support MSI-X, which this change also does not
affect.
BUG=b:162789858
TEST=Boot Linux 5.8; verify existence of /sys/class/rtc/rtc0
TEST=Boot on x86_64 Chromebook; verify IRQ 8 is not used by PCI devices
Change-Id: I39ca6a823914d2d27caec7812b54bf754ac3db9a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2337370
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
For now, this crate simply re-exports all of sys_util, but it will
be updated to provide new interfaces when needed. This is the
first step to making crosvm not directly depend on sys_util, so
that we can make the interface changes we need without fear of
negatively affecting (i.e. completely breaking) other usages
within chromeos.
BUG=b:162363783
TEST=./build_test
Change-Id: I7d0aa3d8a1f66af1c7fee8fd649723ef17027150
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2325168
Tested-by: Michael Hoyle <mikehoyle@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Michael Hoyle <mikehoyle@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Regardless of what image type crosvm is running (kernel or bios), the
acpi tables, mptables, and smbios should all be set since they depend
on vm-initialization-time set values like the cpu count and the
available pci devices. The guest should not have to setup these
structs differently based on the crosvm inputs.
BUG=b:161912521
TEST=Booted cuttlefish with and without uboot
Change-Id: I98eb7176a6822769dcfb32d6decab717d08236e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2325254
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Ram Muthiah <rammuthiah@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Auto-Submit: Ram Muthiah <rammuthiah@google.com>
Allow the caller of generate_pci_root to specify a maximum number of
IRQs to share between all PCI devices, and use this on x86 to limit the
total number of IRQs to fall within the number of interrupts present on
the current kernel APIC implementation.
BUG=b:161745666
BUG=chromium:1109486
TEST=Boot crosvm with many PCI devices
Change-Id: I07f0e4dab97fc952260ecacc2d84c02c77be1309
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2317899
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Lepton Wu <lepton@chromium.org>
Move GuestAddress and GuestMemory to a new crate for VM memory. This
will make separating sys_util and crosvm independent making it easier
to use sys_util functions outside of crosvm.
Change-Id: I12e14948ea85754dfa6267b3a3fb32b77ef6796e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2311251
Auto-Submit: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Regardless of what image type crosvm is running, it must set the cpuid
since the cpuid is not set by software. This missing setting was
preventing uboot from jumping to the 64 bit kernel since it thought
the cpu was not long mode capable.
BUG=b:153027511
TEST=Booted cuttlefish with and without uboot
Change-Id: Ib8902b324532daf2a0e8ff462603207ff0c64bad
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2298171
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Ram Muthiah <rammuthiah@google.com>
io_jail has been migrated to aosp/external/minijail/rust/minijail.
This removes the crosvm copy and updates the references to use the new
location.
BUG=chromium:1096175
TEST=cargo test
Cq-Depend: chromium:2254418
Change-Id: I29d5c6178b6faf5e52671cfbe6fc7e51f0d21dd2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2254298
Tested-by: Allen Webb <allenwebb@google.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Allen Webb <allenwebb@google.com>
Enable support for user provided ACPI tables with supplementary system
description. Argument --acpi-table shall point to exsting file or
pseudo-file with valid ACPI table content.
BUG=None
TEST=boot Linux kernel with generated SSDT tables.
Change-Id: I8eac21da070dcc325884ed888cc7bcb01bc086ce
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2212501
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: Tomasz Jeznach <tjeznach@chromium.org>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Change VolatileSlice so that it is ABI-compatible with iovec. This
allows us to directly pass in a VolatileSlice for a C function that
expects an iovec without having to create temporaries that convert from
one to the other.
Also change all the parameters from u64 to usize. It's not possible to
address more memory than fits into a usize so having u64 here didn't
really provide much benefit and led to a lot of tedious casting back and
forth all over the place.
BUG=none
TEST=unit tests
Cq-Depend: chromium:2206621
Change-Id: I258f9123c603d9a4c6c5e2d4d10eb4aedf74466d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2203998
Tested-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Add the AML support to generate the S1 table instead of hard coding.
Also use the IO allocater to allocate the IO resouce for ACPI PM.
BUG=None
TEST=boot crosvm by command "crosvm run -s crosvm.sock -m 4096 --cpus 4
--rwdisk rootfs.img -p "root=/dev/vda rootfstype=ext4" vmlinux".
Check the S1 capability by "#echo standby > /sys/power/state" from guest
side. Linux guest is suspended. And resume linux guest by "#crosvm resume
crosvm.sock" from host side.
Change-Id: I75b484c44db05f98d49557ba694a1531b57871c1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2119571
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Simple refactor of FDT and MPTables generation to use PCI device
addressing and allow declatation of non-zero PCI bus ids for x86
architectures. It also allows non sequential IRQ allocation for
PCI devices.
BUG=None
TEST=build_test & tast run crostini.Sanity
Change-Id: I6cc31ce412199a732499b2d8d18d99f08d765690
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2175739
Tested-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
This allows the creation of virtio-console devices using the new
hardware=virtio-console parameter to the --serial option.
Also add support for the serial earlycon option, which allows using
virtio-console as the main console device with a traditional serial
device as the early console. This allows logging during early boot
before PCI device discovery (when virtio-console devices are set up).
BUG=chromium:1059924
TEST=crosvm run -r vm_rootfs.img \
--serial hardware=serial,type=stdout,console=false,earlycon=true \
--serial hardware=virtio-console,type=stdout,console=true,stdin=true \
vm_kernel
Change-Id: Iff48800272b154d49b1da00f3914799089268afe
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2127322
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Split the serial code into two parts:
- Configuration and setup: arch/src/serial.rs
- Serial device emulation: devices/src/serial.rs
No change in functionality - this is just preparation for generalizing
the command line parsing/setup code so that it can be used with virtio
console devices as well.
BUG=chromium:1059924
TEST=emerge-nami crosvm
TEST=emerge-kevin crosvm
Change-Id: I0aaf9dd6f8096eac4a17077ab5bf569f57d64ff5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2127319
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Previously the "acpi=off" in cmdline has disabled the ACPI for the
guest kernel. With removing the "acpi=off", the ACPI will be enabled
for the guest kernel by default. With acpi enabled, the SCI irq will
be needed by the ACPI core driver. Register the SCI irq in MP table
so that it can use IO-APIC routing.
The reason to have "pci=noacpi" is that, in the current DSDT there is
only suspend capability, so PCI scan still need to be done by the
traditional way.
BUG=chromium:1018674
TEST=Linux guest is able to boot up with the virtio devices functional.
Also able to see the S1 capability from kernel dmesg.
Change-Id: Id54e788f4aa4c944fac5e3fa1c92b76865dd5021
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2078967
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
rustc now warns about return statements that have an extra set of
parenthesis. Remove such instances so that the code is warning free.
TEST=cargo build completes without warnings
Change-Id: I55148f8aceca8ba90f6bead2b6929e2c843351aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2104767
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Devices use irqfd to inject interrupts, we listen to them in the main
thread and activate userspace pic/ioapic accordingly.
BUG=chromium:908689
TEST=lanuch linux guest with `--split-irqchip` flag
Change-Id: If30d17ce7ec9e26dba782c89cc1b9b2ff897a70d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1945798
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Zhuocheng Ding <zhuocheng.ding@intel.corp-partner.google.com>
S1 is a sleep state which is lighter than S3, but enough to put the devices
into the suspended state.
With this DSDT, the guest kernel is able to see the S1 capability and to
put the VM into virtual S1. During the virtual S1, guest kernel will call
each suspend callbacks of the devices driver to put the devices into the
suspend state, including the pass through device.
BUG=chromium:1018674
TEST=boot linux guest with ACPI enabled, and able to see "shallow" by
"cat /sys/power/mem_sleep", which means the S1
Change-Id: I232609f6f2474895fd9ec4046d88236c413e51af
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2035353
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
sci_irq can be allocated so not to use the fixed number 9.
Actually this irq is not used for injecting any event but
the Linux guest OS requires to see meaning value from the
FADP table. So just fill it to satisfy.
BUG=chromium:1018674
TEST=None
Change-Id: If3ea3bb2844fc7fc1c24a577b7098d2a3e6f1c7f
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2035352
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Add acpi_rsdp_addr in boot_params to allow crosvm to pass
a physicall address of RSDP to the Linux guest kernel, so
that the linux guest kernel can parse the constructed ACPI
tables and enable the ACPI.
Although there is ACPI tables but as we still have "acpi=off"
in command line parameter, there is still no ACPI in guest kernel.
The ACPI construction refers to the implementation of the
Cloud-hypervisor commit:
- arch: x86_64: Generate basic ACPI tables
BUG=chromium:1018674
TEST=None
Change-Id: Ibcb2ae98c43da8ef8c07a07eda9213f61570d14c
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2035351
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Use the Rust __cpuid and __cpuid_count intrinsics to replace the C
implementation in host_cpuid.c.
These are defined in core, but they are also re-exported in std, despite
being undocumented there due to technical reasons:
https://github.com/rust-lang/rust/pull/57808#issuecomment-457390549
Use the std version for consistency (we don't currently use anything
from core anywhere else in crosvm).
BUG=None
TEST=cargo test -p x86_64
TEST=Boot crosvm on x86_64
Change-Id: Ic7a1094d1b804304a2944f8ee1fe55c5e2db23e9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2067159
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This change implements MSI routing and injection, so that service_irq
can actually inject an interrupt into guest.
BUG=chromium:908689
TEST=Unit tests in file.
Change-Id: I2db4f00f569db56f5765c707faaa87c64fd3da9f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1945795
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Zhuocheng Ding <zhuocheng.ding@intel.corp-partner.google.com>
For suspend request from VM, will write suspend event and notify
crosvm main process to pause VCPUs.
For resume request, it is not from VM itself but by the resume
command through crosvm socket. Resume request will notify the PM
device to fill its wakeup registers with wakeup event so that
when VCPUs start to run, VM can know there is wakeup from outside.
BUG=chromium:1018674
TEST=cargo test -p devices
Change-Id: I4724ffee10150065a62bf520076c16cbc70b7749
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2035169
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Add ACPI PM resource emulation code in devices, so that it can support
the ACPI PM requestion from guest OS.
BUG=chromium:1018674
TEST=cargo test -p devices
Change-Id: I7b82b1c3a6f609136e493b55420b947afd1d5cfc
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2035168
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Adds support for pstore on ARCVM on x86_64.
The backend file of the buffer will be passed via argument of the crosvm.
BUG=b:144962428
TEST=kernel crash on eve-arcvm, check /sys/fs/pstore/console-ramoops-0
Launch crostini manually on eve-arcvm
Change-Id: I29492ac7a9067aa2ae23eb03fbb942ab7dd3aa8d
Signed-off-by: Kansho Nishida <kansho@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1973391
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Kansho Nishida <kansho@chromium.org>
