mirror of
https://chromium.googlesource.com/crosvm/crosvm
synced 2024-11-25 05:03:05 +00:00
395340cb39
Bug=b:333885919 Change-Id: I1dd725a45767d2e9306cff71992d73d3405b0ce5 Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/5521716 Reviewed-by: Idan Raiter <idanr@google.com> Commit-Queue: Judson Powers <judsonp@google.com> Reviewed-by: Noah Gold <nkgold@google.com>
475 lines
16 KiB
Rust
475 lines
16 KiB
Rust
// Copyright 2017 The ChromiumOS Authors
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// TODO(b/237714823): Currently, only kvm is enabled for this test once LUCI can run windows.
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#![cfg(any(target_os = "android", target_os = "linux"))]
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#![cfg(target_arch = "x86_64")]
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use std::sync::atomic::AtomicU16;
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use std::sync::atomic::Ordering;
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use hypervisor::*;
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use vm_memory::GuestAddress;
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use vm_memory::GuestMemory;
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#[test]
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#[cfg(any(target_os = "android", target_os = "linux"))]
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fn test_kvm_mmio_and_pio() {
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use hypervisor::kvm::*;
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test_mmio_and_pio(|guest_mem| {
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let kvm = Kvm::new().expect("failed to create kvm");
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let vm = KvmVm::new(&kvm, guest_mem, Default::default()).expect("failed to create vm");
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(kvm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "haxm"))]
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fn test_haxm_mmio_and_pio() {
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use hypervisor::haxm::*;
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test_mmio_and_pio(|guest_mem| {
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let haxm = Haxm::new().expect("failed to create haxm");
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let vm = HaxmVm::new(&haxm, guest_mem).expect("failed to create vm");
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(haxm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "whpx"))]
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fn test_whpx_mmio_and_pio() {
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use hypervisor::whpx::*;
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if !Whpx::is_enabled() {
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return;
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}
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test_mmio_and_pio(|guest_mem| {
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let whpx = Whpx::new().expect("failed to create whpx");
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let vm =
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WhpxVm::new(&whpx, 1, guest_mem, CpuId::new(0), false).expect("failed to create vm");
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(whpx, vm)
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});
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}
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#[test]
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#[cfg(feature = "gvm")]
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fn test_gvm_mmio_and_pio() {
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use hypervisor::gvm::*;
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test_mmio_and_pio(|guest_mem| {
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let gvm = Gvm::new().expect("failed to create gvm");
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let vm = GvmVm::new(&gvm, guest_mem).expect("failed to create vm");
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(gvm, vm)
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});
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}
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fn test_mmio_and_pio<CreateVm, HypervisorT, VmT>(create_vm: CreateVm)
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where
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CreateVm: FnOnce(GuestMemory) -> (HypervisorT, VmT),
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HypervisorT: Hypervisor,
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VmT: VmX86_64,
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{
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/*
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0x0000000000000000: 67 88 03 mov byte ptr [ebx], al
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0x0000000000000003: 67 8A 01 mov al, byte ptr [ecx]
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0x0000000000000006: E6 19 out 0x19, al
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0x0000000000000008: E4 20 in al, 0x20
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0x000000000000000a: F4 hlt
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*/
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let code: [u8; 11] = [
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0x67, 0x88, 0x03, 0x67, 0x8a, 0x01, 0xe6, 0x19, 0xe4, 0x20, 0xf4,
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];
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let mem_size = 0x2000;
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let load_addr = GuestAddress(0x1000);
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let guest_mem =
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GuestMemory::new(&[(GuestAddress(0), mem_size)]).expect("failed to create guest mem");
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guest_mem
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.write_at_addr(&code[..], load_addr)
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.expect("failed to write to guest memory");
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let (_, vm) = create_vm(guest_mem);
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let mut vcpu = vm.create_vcpu(0).expect("new vcpu failed");
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let mut vcpu_sregs = vcpu.get_sregs().expect("get sregs failed");
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vcpu_sregs.cs.base = 0;
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vcpu_sregs.cs.selector = 0;
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vcpu.set_sregs(&vcpu_sregs).expect("set sregs failed");
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let vcpu_regs = Regs {
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rip: load_addr.offset(),
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rflags: 2,
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rax: 0x33,
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rbx: 0x3000,
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rcx: 0x3010,
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..Default::default()
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};
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vcpu.set_regs(&vcpu_regs).expect("set regs failed");
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// Ensure we get exactly 2 exits for the mmio and the pio.
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let exits = AtomicU16::new(0);
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loop {
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match vcpu.run().expect("run failed") {
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VcpuExit::Mmio => {
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vcpu.handle_mmio(&mut |IoParams {
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address,
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size,
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operation,
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}| {
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match operation {
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IoOperation::Read => {
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let mut data = [0u8; 8];
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assert_eq!(address, 0x3010);
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assert_eq!(size, 1);
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exits.fetch_add(1, Ordering::SeqCst);
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// this number will be read into al register
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data.copy_from_slice(&0x66_u64.to_ne_bytes());
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Some(data)
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}
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IoOperation::Write { data } => {
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assert_eq!(address, 0x3000);
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assert_eq!(data[0], 0x33);
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assert_eq!(size, 1);
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exits.fetch_add(1, Ordering::SeqCst);
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None
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}
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}
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})
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.expect("failed to set the data");
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}
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VcpuExit::Io => {
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vcpu.handle_io(&mut |IoParams {
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address,
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size,
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operation,
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}| {
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match operation {
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IoOperation::Read => {
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let mut data = [0u8; 8];
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assert_eq!(address, 0x20);
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assert_eq!(size, 1);
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exits.fetch_add(1, Ordering::SeqCst);
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// this number will be read into the al register
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data.copy_from_slice(&0x77_u64.to_ne_bytes());
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Some(data)
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}
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IoOperation::Write { data } => {
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assert_eq!(address, 0x19);
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assert_eq!(size, 1);
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assert_eq!(data[0], 0x66);
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exits.fetch_add(1, Ordering::SeqCst);
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None
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}
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}
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})
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.expect("failed to set the data");
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}
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VcpuExit::Hlt => {
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break;
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}
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// Continue on external interrupt or signal
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VcpuExit::Intr => continue,
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r => panic!("unexpected exit reason: {:?}", r),
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}
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}
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assert_eq!(exits.load(Ordering::SeqCst), 4);
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let regs: Regs = vcpu.get_regs().expect("failed to get regs");
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assert_eq!(regs.rax, 0x77);
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}
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#[test]
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#[cfg(any(target_os = "android", target_os = "linux"))]
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fn test_kvm_pio_out() {
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use hypervisor::kvm::*;
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test_pio_out(|guest_mem| {
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let kvm = Kvm::new().expect("failed to create kvm");
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let vm = KvmVm::new(&kvm, guest_mem, Default::default()).expect("failed to create vm");
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(kvm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "haxm"))]
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fn test_haxm_pio_out() {
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use hypervisor::haxm::*;
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test_pio_out(|guest_mem| {
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let haxm = Haxm::new().expect("failed to create haxm");
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let vm = HaxmVm::new(&haxm, guest_mem).expect("failed to create vm");
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(haxm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "whpx"))]
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fn test_whpx_pio_out() {
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use hypervisor::whpx::*;
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if !Whpx::is_enabled() {
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return;
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}
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test_pio_out(|guest_mem| {
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let whpx = Whpx::new().expect("failed to create whpx");
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let vm =
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WhpxVm::new(&whpx, 1, guest_mem, CpuId::new(0), false).expect("failed to create vm");
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(whpx, vm)
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});
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}
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#[test]
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#[cfg(feature = "gvm")]
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fn test_gvm_pio_out() {
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use hypervisor::gvm::*;
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test_pio_out(|guest_mem| {
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let gvm = Gvm::new().expect("failed to create gvm");
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let vm = GvmVm::new(&gvm, guest_mem).expect("failed to create vm");
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(gvm, vm)
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});
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}
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fn test_pio_out<CreateVm, HypervisorT, VmT>(create_vm: CreateVm)
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where
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CreateVm: FnOnce(GuestMemory) -> (HypervisorT, VmT),
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HypervisorT: Hypervisor,
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VmT: VmX86_64,
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{
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/*
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0x00: 31 c0 xor ax, ax (ax = 0)
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0x02: 40 inc ax (ax = 1)
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0x03: e7 01 out 0x1, ax (OUT 0x0001 to port 1)
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0x05: 40 inc ax (ax = 2)
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0x06: e6 02 out 0x2, al (OUT 0x02 to port 2)
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0x08: 40 inc ax (ax = 3)
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0x09: 89 c2 mov dx, ax (dx = 3)
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0x0b: ef out dx, ax (OUT 0x0003 to port 3)
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0x0c: 40 inc ax (ax = 4)
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0x0d: 42 inc dx (dx = 4)
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0x0e: ee out dx, al (OUT 0x04 to port 4)
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0x0f: f4 hlt
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*/
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let code: [u8; 16] = [
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0x31, 0xc0, 0x40, 0xe7, 0x01, 0x40, 0xe6, 0x02, 0x40, 0x89, 0xc2, 0xef, 0x40, 0x42, 0xee,
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0xf4,
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];
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let mem_size = 0x2000;
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let load_addr = GuestAddress(0x1000);
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let guest_mem =
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GuestMemory::new(&[(GuestAddress(0), mem_size)]).expect("failed to create guest mem");
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guest_mem
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.write_at_addr(&code[..], load_addr)
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.expect("failed to write to guest memory");
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let (_, vm) = create_vm(guest_mem);
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let mut vcpu = vm.create_vcpu(0).expect("new vcpu failed");
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let mut vcpu_sregs = vcpu.get_sregs().expect("get sregs failed");
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vcpu_sregs.cs.base = 0;
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vcpu_sregs.cs.selector = 0;
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vcpu.set_sregs(&vcpu_sregs).expect("set sregs failed");
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let vcpu_regs = Regs {
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rip: load_addr.offset(),
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rflags: 2,
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..Default::default()
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};
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vcpu.set_regs(&vcpu_regs).expect("set regs failed");
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// Ensure we get the expected PIO exits
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let exit_count = AtomicU16::new(0);
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let exit_bits = AtomicU16::new(0);
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loop {
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match vcpu.run().expect("run failed") {
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VcpuExit::Io => {
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vcpu.handle_io(&mut |IoParams {
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address,
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size,
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operation,
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}| {
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match operation {
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IoOperation::Read => panic!("unexpected PIO read"),
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IoOperation::Write { data } => {
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assert!((1..=4).contains(&address));
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if address % 2 == 0 {
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assert_eq!(size, 1);
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assert_eq!(data[0], address as u8);
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} else {
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assert_eq!(size, 2);
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assert_eq!(data[0], address as u8);
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assert_eq!(data[1], 0);
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}
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exit_bits.fetch_or(1 << (address - 1), Ordering::SeqCst);
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exit_count.fetch_add(1, Ordering::SeqCst);
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None
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}
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}
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})
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.expect("failed to set the data");
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}
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VcpuExit::Hlt => {
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break;
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}
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// Continue on external interrupt or signal
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VcpuExit::Intr => continue,
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r => panic!("unexpected exit reason: {:?}", r),
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}
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}
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// bits 0 through 3 have been set
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assert_eq!(exit_bits.load(Ordering::SeqCst), 0xf);
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assert_eq!(exit_count.load(Ordering::SeqCst), 4);
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}
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#[test]
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#[cfg(any(target_os = "android", target_os = "linux"))]
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fn test_kvm_pio_in() {
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use hypervisor::kvm::*;
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test_pio_in(|guest_mem| {
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let kvm = Kvm::new().expect("failed to create kvm");
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let vm = KvmVm::new(&kvm, guest_mem, Default::default()).expect("failed to create vm");
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(kvm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "haxm"))]
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fn test_haxm_pio_in() {
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use hypervisor::haxm::*;
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test_pio_in(|guest_mem| {
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let haxm = Haxm::new().expect("failed to create haxm");
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let vm = HaxmVm::new(&haxm, guest_mem).expect("failed to create vm");
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(haxm, vm)
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});
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}
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#[test]
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#[cfg(all(windows, feature = "whpx"))]
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fn test_whpx_pio_in() {
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use hypervisor::whpx::*;
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if !Whpx::is_enabled() {
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return;
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}
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test_pio_in(|guest_mem| {
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let whpx = Whpx::new().expect("failed to create whpx");
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let vm =
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WhpxVm::new(&whpx, 1, guest_mem, CpuId::new(0), false).expect("failed to create vm");
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(whpx, vm)
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});
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}
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#[test]
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#[cfg(feature = "gvm")]
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fn test_gvm_pio_in() {
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use hypervisor::gvm::*;
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test_pio_in(|guest_mem| {
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let gvm = Gvm::new().expect("failed to create gvm");
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let vm = GvmVm::new(&gvm, guest_mem).expect("failed to create vm");
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(gvm, vm)
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});
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}
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fn test_pio_in<CreateVm, HypervisorT, VmT>(create_vm: CreateVm)
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where
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CreateVm: FnOnce(GuestMemory) -> (HypervisorT, VmT),
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HypervisorT: Hypervisor,
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VmT: VmX86_64,
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{
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/*
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0x00: e5 01 in ax, 0x1 (IN 16 bits from port 1)
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0x02: 89 c6 mov si, ax (si = value from port 1)
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0x04: 31 c0 xor ax, ax (clear ax, since IN will only write the lower byte)
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0x06: e4 02 in al, 0x02 (IN 8 bits from port 2)
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0x08: 89 c3 mov bx, ax (bx = value from port 2)
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0x0a: ba 03 00 mov dx, 0x03 (dx = 3)
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0x0d: ed in ax, dx (IN 16 bits from port 3)
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0x0e: 89 c1 mov cx, ax (cx = value from port 3)
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0x10: 42 inc dx (dx = 4)
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0x11: 31 c0 xor ax, ax (clear ax, since IN will only write the lower byte)
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0x13: ec in al, dx (IN 8 bits from port 4)
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0x14: 89 c2 mov dx, ax (dx = value from port 4)
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0x16: 89 f0 mov ax, si (ax = value from port 1)
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0x18: f4 hlt
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*/
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let code: [u8; 25] = [
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0xe5, 0x01, 0x89, 0xc6, 0x31, 0xc0, 0xe4, 0x02, 0x89, 0xc3, 0xba, 0x03, 0x00, 0xed, 0x89,
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0xc1, 0x42, 0x31, 0xc0, 0xec, 0x89, 0xc2, 0x89, 0xf0, 0xf4,
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];
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let mem_size = 0x2000;
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let load_addr = GuestAddress(0x1000);
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let guest_mem =
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GuestMemory::new(&[(GuestAddress(0), mem_size)]).expect("failed to create guest mem");
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guest_mem
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.write_at_addr(&code[..], load_addr)
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.expect("failed to write to guest memory");
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let (_, vm) = create_vm(guest_mem);
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let mut vcpu = vm.create_vcpu(0).expect("new vcpu failed");
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let mut vcpu_sregs = vcpu.get_sregs().expect("get sregs failed");
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vcpu_sregs.cs.base = 0;
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vcpu_sregs.cs.selector = 0;
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vcpu.set_sregs(&vcpu_sregs).expect("set sregs failed");
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let vcpu_regs = Regs {
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rip: load_addr.offset(),
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rflags: 2,
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..Default::default()
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};
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vcpu.set_regs(&vcpu_regs).expect("set regs failed");
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// Ensure we get the expected PIO exits
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let exit_count = AtomicU16::new(0);
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let exit_bits = AtomicU16::new(0);
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loop {
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match vcpu.run().expect("run failed") {
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VcpuExit::Io => {
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vcpu.handle_io(&mut |IoParams {
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address,
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size,
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operation,
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}| {
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match operation {
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IoOperation::Read => {
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let mut data = [0u8; 8];
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assert!((1..=4).contains(&address));
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if address % 2 == 0 {
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assert_eq!(size, 1);
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data[0] = address as u8;
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} else {
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assert_eq!(size, 2);
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data[0] = address as u8;
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data[1] = address as u8;
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}
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exit_bits.fetch_or(1 << (address - 1), Ordering::SeqCst);
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exit_count.fetch_add(1, Ordering::SeqCst);
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Some(data)
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}
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IoOperation::Write { .. } => panic!("unexpected PIO write"),
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}
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})
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.expect("failed to set the data");
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}
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VcpuExit::Hlt => {
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break;
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}
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// Continue on external interrupt or signal
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VcpuExit::Intr => continue,
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r => panic!("unexpected exit reason: {:?}", r),
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}
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}
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// bits 0 through 3 have been set
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assert_eq!(exit_bits.load(Ordering::SeqCst), 0xf);
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assert_eq!(exit_count.load(Ordering::SeqCst), 4);
|
|
let regs: Regs = vcpu.get_regs().expect("failed to get regs");
|
|
assert_eq!(regs.rax, 0x0101);
|
|
assert_eq!(regs.rbx, 0x02);
|
|
assert_eq!(regs.rcx, 0x0303);
|
|
assert_eq!(regs.rdx, 0x04);
|
|
}
|